diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index 7e4b36f7e5..8a1adfe802 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -118,8 +118,10 @@ Wavefront::initRegState(HSAQueueEntry *task, int wgSizeInWorkItems)
 {
     int regInitIdx = 0;
 
-    // iterate over all the init fields and check which
-    // bits are enabled
+    // Iterate over all the init fields and check which
+    // bits are enabled. Useful information can be found here:
+    // https://github.com/ROCm-Developer-Tools/ROCm-ComputeABI-Doc/
+    //                    blob/master/AMDGPU-ABI.md
     for (int en_bit = 0; en_bit < NumScalarInitFields; ++en_bit) {
 
         if (task->sgprBitEnabled(en_bit)) {
@@ -263,6 +265,12 @@ Wavefront::initRegState(HSAQueueEntry *task, int wgSizeInWorkItems)
                         computeUnit->cu_id, simdId,
                         wfSlotId, wfDynId, physSgprIdx,
                         task->dispatchId());
+
+                // Dispatch ID in gem5 is an int. Set upper 32-bits to zero.
+                physSgprIdx
+                    = computeUnit->registerManager->mapSgpr(this, regInitIdx);
+                computeUnit->srf[simdId]->write(physSgprIdx, 0);
+                ++regInitIdx;
                 break;
               case FlatScratchInit:
                 physSgprIdx