split uart into urt8250 and uart8530

fix some doxygen comments

SConscript:
    Added split uart files
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/tsunami.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/tsunamireg.h:
    fix doxgyen file comment
dev/uart.cc:
dev/uart.hh:
python/m5/objects/Uart.py:
    split uart into urt8250 and uart8530

--HG--
extra : convert_revision : 2e70aad892a37620d7909017648bca6d7d69d678
This commit is contained in:
Ali Saidi
2005-06-05 01:22:21 -04:00
parent 8bbaaa7478
commit adce616cfe
14 changed files with 469 additions and 436 deletions

View File

@@ -26,14 +26,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* @file
* Defines a 8250 UART
/** @file
* Base class for UART
*/
#ifndef __TSUNAMI_UART_HH__
#define __TSUNAMI_UART_HH__
#ifndef __UART_HH__
#define __UART_HH__
#include "dev/tsunamireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
@@ -47,45 +46,25 @@ const int TX_INT = 0x2;
class Uart : public PioDevice
{
private:
protected:
int status;
Addr addr;
Addr size;
SimConsole *cons;
protected:
int readAddr; // tlaser only
uint8_t IER, DLAB, LCR, MCR;
int status;
class IntrEvent : public Event
{
protected:
Uart *uart;
int intrBit;
public:
IntrEvent(Uart *u, int bit);
virtual void process();
virtual const char *description();
void scheduleIntr();
};
IntrEvent txIntrEvent;
IntrEvent rxIntrEvent;
public:
Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
Fault read(MemReqPtr &req, uint8_t *data);
Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
/**
* Inform the uart that there is data available.
*/
void dataAvailable();
virtual void dataAvailable() = 0;
/**
@@ -94,9 +73,6 @@ class Uart : public PioDevice
*/
bool intStatus() { return status ? true : false; }
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Return how long this access will take.
* @param req the memory request to calcuate
@@ -105,4 +81,4 @@ class Uart : public PioDevice
Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_UART_HH__
#endif // __UART_HH__