From ad8c4f1bf422762a138cb038696f750d939fe00e Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 1 Mar 2023 13:52:49 +0100 Subject: [PATCH] stdlib: Use get_mem_ports in incorporate caches Make use of get_mem_ports() method of the AbstractMemorySystem interface when incorporating caches to prevent the usage of the hard-coded memory port name "port" as some memory controllers do not have a port with this exact name. Change-Id: Ic7480166b257c6d356027234758b65b0a97995e3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68482 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- .../gem5/components/cachehierarchies/classic/no_cache.py | 4 ++-- .../cachehierarchies/classic/private_l1_cache_hierarchy.py | 4 ++-- .../classic/private_l1_private_l2_cache_hierarchy.py | 4 ++-- .../classic/private_l1_shared_l2_cache_hierarchy.py | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/classic/no_cache.py b/src/python/gem5/components/cachehierarchies/classic/no_cache.py index f3bbdcdf74..51b5d30eb4 100644 --- a/src/python/gem5/components/cachehierarchies/classic/no_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py @@ -119,8 +119,8 @@ class NoCache(AbstractClassicCacheHierarchy): # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port def _setup_coherent_io_bridge(self, board: AbstractBoard) -> None: """Create a bridge from I/O back to membus""" diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py index dc44c9e016..42ff183a1d 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py @@ -90,8 +90,8 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy): # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port self.l1icaches = [ L1ICache(size=self._l1i_size) diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index f10828b9c2..8b60aef7f6 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -115,8 +115,8 @@ class PrivateL1PrivateL2CacheHierarchy( # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port self.l1icaches = [ L1ICache(size=self._l1i_size) diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py index 602c99c686..72df1a53de 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py @@ -111,8 +111,8 @@ class PrivateL1SharedL2CacheHierarchy( # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port self.l1icaches = [ L1ICache(