From ac250beb73d14fd68d514059aeb64458f3966644 Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan@linux.ibm.com>
Date: Sat, 6 Feb 2021 17:17:16 +0530
Subject: [PATCH] arch-power: Add doubleword load-store instructions

This introduces new formats for DS form instructions and
adds the following instructions.
  * Load Doubleword (ld)
  * Load Doubleword Indexed (ldx)
  * Load Doubleword with Update (ldu)
  * Load Doubleword with Update Indexed (ldux)
  * Store Doubleword (std)
  * Store Doubleword Indexed (stdx)
  * Store Doubleword with Update (stdu)
  * Store Doubleword with Update Indexed (stdux)

Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40895
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: lkcl <luke.leighton@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/power/isa/decoder.isa     | 16 +++++++++++-
 src/arch/power/isa/formats/mem.isa | 42 ++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index c81e65be46..d0d3dc93ed 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -201,6 +201,7 @@ decode PO default Unknown::unknown() {
                 Rsv = 1; RsvLen = 4; RsvAddr = EA;
             }});
 
+            21: ldx({{ Rt = Mem; }});
             23: lwzx({{ Rt = Mem_uw; }});
         }
 
@@ -223,6 +224,7 @@ decode PO default Unknown::unknown() {
             CR = insertCRField(CR, BF, cr);
         }});
 
+        53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
         55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
         60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
         87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
@@ -230,6 +232,7 @@ decode PO default Unknown::unknown() {
         124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
 
         format StoreIndexOp {
+            149: stdx({{ Mem = Rs }});
             150: stwcx({{
                 bool store_performed = false;
                 Mem_uw = Rs_uw;
@@ -250,7 +253,11 @@ decode PO default Unknown::unknown() {
             151: stwx({{ Mem_uw = Rs_uw; }});
         }
 
-        183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
+        format StoreIndexUpdateOp {
+            181: stdux({{ Mem = Rs; }});
+            183: stwux({{ Mem_uw = Rs_uw; }});
+        }
+
         215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
         246: MiscOp::dcbtst({{ }});
         247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
@@ -543,6 +550,8 @@ decode PO default Unknown::unknown() {
     55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});
 
     58: decode DS_XO {
+        0: LoadDispShiftOp::ld({{ Rt = Mem; }});
+        1: LoadDispShiftUpdateOp::ldu({{ Rt = Mem; }});
         2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
     }
 
@@ -559,6 +568,11 @@ decode PO default Unknown::unknown() {
         }
     }
 
+    62: decode DS_XO {
+        0: StoreDispShiftOp::std({{ Mem = Rs; }});
+        1: StoreDispShiftUpdateOp::stdu({{ Mem = Rs; }});
+    }
+
     63: decode A_XO {
         format FloatArithOp {
             20: fsub({{ Ft = Fa - Fb; }});
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index d2b3ab7cab..488629643f 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -311,6 +311,16 @@ def format LoadDispShiftOp(memacc_code,
 }};
 
 
+def format StoreDispShiftOp(memacc_code,
+                            ea_code = {{ EA = Ra + (ds << 2); }},
+                            ea_code_ra0 = {{ EA = (ds << 2); }},
+                            mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+                 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
 def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }},
                             mem_flags = [], inst_flags = []) {{
 
@@ -339,3 +349,35 @@ def format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }},
                       decode_template = CheckRaZeroDecode,
                       exec_template_base = 'Store')
 }};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+                                 ea_code = {{ EA = Ra + (ds << 2); }},
+                                 mem_flags = [], inst_flags = []) {{
+
+    # Add in the update code
+    memacc_code += 'Ra = EA;'
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      base_class = 'MemDispShiftOp',
+                      decode_template = CheckRaRtDecode,
+                      exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+                                  ea_code = {{ EA = Ra + (ds << 2); }},
+                                  mem_flags = [], inst_flags = []) {{
+
+    # Add in the update code
+    memacc_code += 'Ra = EA;'
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      base_class = 'MemDispShiftOp',
+                      decode_template = CheckRaZeroDecode,
+                      exec_template_base = 'Store')
+}};