From abdf573c5319bbab16ace5264628cda57ac11170 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabe.black@gmail.com>
Date: Sat, 21 Aug 2021 06:06:22 -0700
Subject: [PATCH] arch-power: Use the OperandDesc classes in the ISA
 description.

Change-Id: I7c46d97f581cd114dcdc8061fa555d5ac927aa2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49730
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/power/isa/operands.isa | 46 ++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 765391eca1..979506ebd2 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -42,39 +42,39 @@ def operand_types {{
 
 def operands {{
     # General Purpose Integer Reg Operands
-    'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
-    'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
-    'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
-    'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
-    'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),
+    'Rs': IntRegOp('ud', 'RS', 'IsInteger', 1),
+    'Ra': IntRegOp('ud', 'RA', 'IsInteger', 2),
+    'Rb': IntRegOp('ud', 'RB', 'IsInteger', 3),
+    'Rc': IntRegOp('ud', 'RC', 'IsInteger', 4),
+    'Rt': IntRegOp('ud', 'RT', 'IsInteger', 5),
 
     # General Purpose Floating Point Reg Operands
-    'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
-    'Fb': ('FloatReg', 'df', 'FRB', 'IsFloating', 2),
-    'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
-    'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
-    'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
+    'Fa': FloatRegOp('df', 'FRA', 'IsFloating', 1),
+    'Fb': FloatRegOp('df', 'FRB', 'IsFloating', 2),
+    'Fc': FloatRegOp('df', 'FRC', 'IsFloating', 3),
+    'Fs': FloatRegOp('df', 'FRS', 'IsFloating', 4),
+    'Ft': FloatRegOp('df', 'FRT', 'IsFloating', 5),
 
     # Memory Operand
-    'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 8),
+    'Mem': MemOp('ud', None, (None, 'IsLoad', 'IsStore'), 8),
 
     # Program counter and next
-    'CIA': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 9),
-    'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),
+    'CIA': PCStateOp('ud', 'pc', (None, None, 'IsControl'), 9),
+    'NIA': PCStateOp('ud', 'npc', (None, None, 'IsControl'), 9),
 
     # Control registers
-    'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
-    'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
-    'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
-    'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
-    'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
-    'MSR': ('IntReg', 'ud', 'INTREG_MSR', 'IsInteger', 9),
+    'CR': IntRegOp('uw', 'INTREG_CR', 'IsInteger', 9),
+    'LR': IntRegOp('ud', 'INTREG_LR', 'IsInteger', 9),
+    'CTR': IntRegOp('ud', 'INTREG_CTR', 'IsInteger', 9),
+    'TAR': IntRegOp('ud', 'INTREG_TAR', 'IsInteger', 9),
+    'XER': IntRegOp('uw', 'INTREG_XER', 'IsInteger', 9),
+    'MSR': IntRegOp('ud', 'INTREG_MSR', 'IsInteger', 9),
 
     # Setting as IntReg so things are stored as an integer, not double
-    'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
+    'FPSCR': IntRegOp('uw', 'INTREG_FPSCR', 'IsFloating', 9),
 
     # Registers for linked loads and stores
-    'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
-    'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
-    'RsvAddr': ('IntReg', 'ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
+    'Rsv': IntRegOp('uw', 'INTREG_RSV', 'IsInteger', 9),
+    'RsvLen': IntRegOp('uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
+    'RsvAddr': IntRegOp('ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
 }};