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Major changes to how SimObjects are created and initialized. Almost all

Browse Source 
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
This commit is contained in:
Nathan Binkert
2007-07-23 21:51:38 -07:00
parent 552097b92e
commit abc76f20cb
136 changed files with 2044 additions and 6740 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/dev/Ethernet.py
View File

@@ -180,6 +180,8 @@ class SinicPciData(PciConfigData):
class Sinic(EtherDevBase):
type = 'Sinic'
cxx_namespace = 'Sinic'
cxx_class = 'Device'
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
@@ -197,4 +199,7 @@ class Sinic(EtherDevBase):
class SinicInt(EtherInt):
type = 'SinicInt'
cxx_namespace = 'Sinic'
cxx_class = 'Interface'
device = Param.Sinic("Ethernet device of this interface")

4
src/dev/SConscript
View File

@@ -50,7 +50,7 @@ if env['FULL_SYSTEM']:
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
Source('ethertap.cc')
Source('ethertap.cc')
Source('i8254xGBe.cc')
Source('ide_ctrl.cc')
Source('ide_disk.cc')
@@ -63,6 +63,6 @@ if env['FULL_SYSTEM']:
Source('platform.cc')
Source('simconsole.cc')
Source('simple_disk.cc')
#Source('sinic.cc')
Source('sinic.cc')
Source('uart.cc')
Source('uart8250.cc')

49
src/dev/alpha/console.cc
View File

@@ -51,15 +51,15 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
#include "sim/builder.hh"
#include "params/AlphaConsole.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace AlphaISA;
AlphaConsole::AlphaConsole(Params *p)
: BasicPioDevice(p), disk(p->disk),
console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
AlphaConsole::AlphaConsole(const Params *p)
: BasicPioDevice(p), disk(p->disk), console(p->sim_console),
system(p->system), cpu(p->cpu)
{
pioSize = sizeof(struct AlphaAccess);
@@ -306,43 +306,8 @@ AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
alphaAccess->unserialize(cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
SimObjectParam<SimConsole *> sim_console;
SimObjectParam<SimpleDisk *> disk;
Param<Addr> pio_addr;
SimObjectParam<AlphaSystem *> system;
SimObjectParam<BaseCPU *> cpu;
SimObjectParam<Platform *> platform;
Param<Tick> pio_latency;
END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
INIT_PARAM(sim_console, "The Simulator Console"),
INIT_PARAM(disk, "Simple Disk"),
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu, "Processor"),
INIT_PARAM(platform, "platform"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
CREATE_SIM_OBJECT(AlphaConsole)
AlphaConsole *
AlphaConsoleParams::create()
{
AlphaConsole::Params *p = new AlphaConsole::Params;
p->name = getInstanceName();
p->platform = platform;
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->cons = sim_console;
p->disk = disk;
p->alpha_sys = system;
p->system = system;
p->cpu = cpu;
return new AlphaConsole(p);
return new AlphaConsole(this);
}
REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)

21
src/dev/alpha/console.hh
View File

@@ -38,6 +38,7 @@
#include "base/range.hh"
#include "dev/alpha/access.h"
#include "dev/io_device.hh"
#include "params/AlphaConsole.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
@@ -98,20 +99,14 @@ class AlphaConsole : public BasicPioDevice
BaseCPU *cpu;
public:
struct Params : public BasicPioDevice::Params
typedef AlphaConsoleParams Params;
AlphaConsole(const Params *p);
const Params *
params() const
{
SimConsole *cons;
SimpleDisk *disk;
AlphaSystem *alpha_sys;
BaseCPU *cpu;
};
protected:
const Params *params() const {return (const Params *)_params; }
public:
/** Standard Constructor */
AlphaConsole(Params *p);
return dynamic_cast<const Params *>(_params);
}
virtual void startup();

23
src/dev/alpha/tsunami.cc
View File

@@ -42,7 +42,7 @@
#include "dev/alpha/tsunami_pchip.hh"
#include "dev/alpha/tsunami_io.hh"
#include "dev/alpha/tsunami.hh"
#include "sim/builder.hh"
#include "params/Tsunami.hh"
#include "sim/system.hh"
using namespace std;
@@ -114,23 +114,8 @@ Tsunami::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
SimObjectParam<System *> system;
SimObjectParam<IntrControl *> intrctrl;
END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
INIT_PARAM(system, "system"),
INIT_PARAM(intrctrl, "interrupt controller")
END_INIT_SIM_OBJECT_PARAMS(Tsunami)
CREATE_SIM_OBJECT(Tsunami)
Tsunami *
TsunamiParams::create()
{
return new Tsunami(getInstanceName(), system, intrctrl);
return new Tsunami(name, system, intrctrl);
}
REGISTER_SIM_OBJECT("Tsunami", Tsunami)

38
src/dev/alpha/tsunami_cchip.cc
View File

@@ -47,14 +47,14 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "params/TsunamiCChip.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiCChip::TsunamiCChip(Params *p)
TsunamiCChip::TsunamiCChip(const Params *p)
: BasicPioDevice(p), tsunami(p->tsunami)
{
pioSize = 0x10000000;
@@ -522,36 +522,8 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(drir);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
CREATE_SIM_OBJECT(TsunamiCChip)
TsunamiCChip *
TsunamiCChipParams::create()
{
TsunamiCChip::Params *p = new TsunamiCChip::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->tsunami = tsunami;
return new TsunamiCChip(p);
return new TsunamiCChip(this);
}
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

21
src/dev/alpha/tsunami_cchip.hh
View File

@@ -35,10 +35,10 @@
#ifndef __TSUNAMI_CCHIP_HH__
#define __TSUNAMI_CCHIP_HH__
#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
#include "params/TsunamiCChip.hh"
/**
* Tsunami CChip CSR Emulation. This device includes all the interrupt
@@ -79,20 +79,19 @@ class TsunamiCChip : public BasicPioDevice
uint64_t itint;
public:
struct Params : public BasicPioDevice::Params
{
Tsunami *tsunami;
};
protected:
const Params *params() const {return (const Params *)_params; }
public:
typedef TsunamiCChipParams Params;
/**
* Initialize the Tsunami CChip by setting all of the
* device register to 0.
* @param p params struct
*/
TsunamiCChip(Params *p);
TsunamiCChip(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);

77
src/dev/alpha/tsunami_io.cc
View File

@@ -40,6 +40,7 @@
#include <string>
#include <vector>
#include "base/time.hh"
#include "base/trace.hh"
#include "dev/pitreg.h"
#include "dev/rtcreg.h"
@@ -50,27 +51,23 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
bool bcd, Tick i)
: _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd)
TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami,
const TsunamiIO::Params *p)
: _name(n), event(tsunami, p->frequency), addr(0)
{
memset(clock_data, 0, sizeof(clock_data));
stat_regA = RTCA_32768HZ | RTCA_1024HZ;
stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
struct tm tm;
parseTime(t, &tm);
year = p->time.tm_year;
year = tm.tm_year;
if (year_is_bcd) {
if (p->year_is_bcd) {
// The datasheet says that the year field can be either BCD or
// years since 1900. Linux seems to be happy with years since
// 1900.
@@ -81,16 +78,16 @@ TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
}
// Unix is 0-11 for month, data seet says start at 1
mon = tm.tm_mon + 1;
mday = tm.tm_mday;
hour = tm.tm_hour;
min = tm.tm_min;
sec = tm.tm_sec;
mon = p->time.tm_mon + 1;
mday = p->time.tm_mday;
hour = p->time.tm_hour;
min = p->time.tm_min;
sec = p->time.tm_sec;
// Datasheet says 1 is sunday
wday = tm.tm_wday + 1;
wday = p->time.tm_wday + 1;
DPRINTFN("Real-time clock set to %s", asctime(&tm));
DPRINTFN("Real-time clock set to %s", asctime(&p->time));
}
void
@@ -437,10 +434,9 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
return "tsunami 8254 Interval timer";
}
TsunamiIO::TsunamiIO(Params *p)
TsunamiIO::TsunamiIO(const Params *p)
: BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd,
p->frequency)
rtc(p->name + ".rtc", p->tsunami, p)
{
pioSize = 0x100;
@@ -658,45 +654,8 @@ TsunamiIO::unserialize(Checkpoint *cp, const string &section)
rtc.unserialize("rtc", cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
Param<Tick> frequency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
VectorParam<int> time;
Param<bool> year_is_bcd;
SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(frequency, "clock interrupt frequency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(time, "System time to use (0 for actual time"),
INIT_PARAM(year_is_bcd, ""),
INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
CREATE_SIM_OBJECT(TsunamiIO)
TsunamiIO *
TsunamiIOParams::create()
{
TsunamiIO::Params *p = new TsunamiIO::Params;
p->frequency = frequency;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->init_time = time;
p->year_is_bcd = year_is_bcd;
p->tsunami = tsunami;
return new TsunamiIO(p);
return new TsunamiIO(this);
}
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)

28
src/dev/alpha/tsunami_io.hh
View File

@@ -37,9 +37,10 @@
#ifndef __DEV_TSUNAMI_IO_HH__
#define __DEV_TSUNAMI_IO_HH__
#include "dev/io_device.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
#include "params/TsunamiIO.hh"
#include "sim/eventq.hh"
/**
@@ -85,9 +86,6 @@ class TsunamiIO : public BasicPioDevice
/** Current RTC register address/index */
int addr;
/** should the year be interpreted as BCD? */
bool year_is_bcd;
/** Data for real-time clock function */
union {
uint8_t clock_data[10];
@@ -114,7 +112,7 @@ class TsunamiIO : public BasicPioDevice
public:
RTC(const std::string &name, Tsunami* tsunami,
const std::vector<int> &t, bool bcd, Tick i);
const TsunamiIOParams *params);
/** RTC address port: write address of RTC RAM data to access */
void writeAddr(const uint8_t data);
@@ -313,23 +311,19 @@ class TsunamiIO : public BasicPioDevice
*/
Tick frequency() const;
struct Params : public BasicPioDevice::Params
{
Tick frequency;
Tsunami *tsunami;
std::vector<int> init_time;
bool year_is_bcd;
};
protected:
const Params *params() const { return (const Params*)_params; }
public:
typedef TsunamiIOParams Params;
/**
* Initialize all the data for devices supported by Tsunami I/O.
* @param p pointer to Params struct
*/
TsunamiIO(Params *p);
TsunamiIO(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

37
src/dev/alpha/tsunami_pchip.cc
View File

@@ -43,14 +43,13 @@
#include "dev/alpha/tsunami.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiPChip::TsunamiPChip(Params *p)
TsunamiPChip::TsunamiPChip(const Params *p)
: BasicPioDevice(p)
{
pioSize = 0x1000;
@@ -334,36 +333,8 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
TsunamiPChip *
TsunamiPChipParams::create()
{
TsunamiPChip::Params *p = new TsunamiPChip::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->tsunami = tsunami;
return new TsunamiPChip(p);
return new TsunamiPChip(this);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

20
src/dev/alpha/tsunami_pchip.hh
View File

@@ -35,9 +35,10 @@
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
#include "params/TsunamiPChip.hh"
/**
* A very simple implementation of the Tsunami PCI interface chips.
@@ -61,19 +62,18 @@ class TsunamiPChip : public BasicPioDevice
uint64_t tba[4];
public:
struct Params : public BasicPioDevice::Params
{
Tsunami *tsunami;
};
protected:
const Params *params() const { return (const Params*)_params; }
public:
typedef TsunamiPChipParams Params;
/**
* Register the PChip with the mmu and init all wsba, wsm, and tba to 0
* @param p pointer to the parameters struct
*/
TsunamiPChip(Params *p);
TsunamiPChip(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/**
* Translate a PCI bus address to a memory address for DMA.

38
src/dev/baddev.cc
View File

@@ -40,14 +40,14 @@
#include "dev/baddev.hh"
#include "dev/platform.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "params/BadDevice.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
BadDevice::BadDevice(Params *p)
: BasicPioDevice(p), devname(p->device_name)
: BasicPioDevice(p), devname(p->devicename)
{
pioSize = 0x10;
}
@@ -66,36 +66,8 @@ BadDevice::write(PacketPtr pkt)
M5_DUMMY_RETURN
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
Param<string> devicename;
Param<Addr> pio_addr;
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> pio_latency;
END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
INIT_PARAM(devicename, "Name of device to error on"),
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(system, "system object"),
INIT_PARAM(platform, "platform"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
END_INIT_SIM_OBJECT_PARAMS(BadDevice)
CREATE_SIM_OBJECT(BadDevice)
BadDevice *
BadDeviceParams::create()
{
BadDevice::Params *p = new BadDevice::Params;
p->name =getInstanceName();
p->platform = platform;
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->system = system;
p->device_name = devicename;
return new BadDevice(p);
return new BadDevice(this);
}
REGISTER_SIM_OBJECT("BadDevice", BadDevice)

14
src/dev/baddev.hh
View File

@@ -38,7 +38,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "params/BadDevice.hh"
/**
* BadDevice
@@ -52,12 +52,14 @@ class BadDevice : public BasicPioDevice
std::string devname;
public:
struct Params : public BasicPioDevice::Params
{
std::string device_name;
};
typedef BadDeviceParams Params;
protected:
const Params *params() const { return (const Params *)_params; }
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
public:
/**

56
src/dev/disk_image.cc
View File

@@ -45,7 +45,8 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "dev/disk_image.hh"
#include "sim/builder.hh"
#include "params/CowDiskImage.hh"
#include "params/RawDiskImage.hh"
#include "sim/sim_exit.hh"
#include "sim/byteswap.hh"
@@ -143,30 +144,12 @@ RawDiskImage::write(const uint8_t *data, off_t offset)
return stream.tellp() - pos;
}
DEFINE_SIM_OBJECT_CLASS_NAME("DiskImage", DiskImage)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
Param<string> image_file;
Param<bool> read_only;
END_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
BEGIN_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
INIT_PARAM(image_file, "disk image file"),
INIT_PARAM_DFLT(read_only, "read only image", false)
END_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
CREATE_SIM_OBJECT(RawDiskImage)
RawDiskImage *
RawDiskImageParams::create()
{
return new RawDiskImage(getInstanceName(), image_file, read_only);
return new RawDiskImage(name, image_file, read_only);
}
REGISTER_SIM_OBJECT("RawDiskImage", RawDiskImage)
////////////////////////////////////////////////////////////////////////
//
// Copy on Write Disk image
@@ -440,33 +423,12 @@ CowDiskImage::unserialize(Checkpoint *cp, const string &section)
open(cowFilename);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
SimObjectParam<DiskImage *> child;
Param<string> image_file;
Param<int> table_size;
Param<bool> read_only;
END_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
BEGIN_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
INIT_PARAM(child, "child image"),
INIT_PARAM_DFLT(image_file, "disk image file", ""),
INIT_PARAM_DFLT(table_size, "initial table size", 65536),
INIT_PARAM_DFLT(read_only, "don't write back to the copy-on-write file",
true)
END_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
CREATE_SIM_OBJECT(CowDiskImage)
CowDiskImage *
CowDiskImageParams::create()
{
if (((string)image_file).empty())
return new CowDiskImage(getInstanceName(), child, table_size);
return new CowDiskImage(name, child, table_size);
else
return new CowDiskImage(getInstanceName(), child, table_size,
return new CowDiskImage(name, child, table_size,
image_file, read_only);
}
REGISTER_SIM_OBJECT("CowDiskImage", CowDiskImage)

25
src/dev/etherbus.cc
View File

@@ -42,7 +42,7 @@
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "sim/builder.hh"
#include "params/EtherBus.hh"
#include "sim/core.hh"
using namespace std;
@@ -103,25 +103,8 @@ EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
return true;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
Param<bool> loopback;
Param<double> speed;
SimObjectParam<EtherDump *> packet_dump;
END_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherBus)
INIT_PARAM(loopback, "send the packet back to the sending interface"),
INIT_PARAM(speed, "bus speed in ticks per byte"),
INIT_PARAM(packet_dump, "object to dump network packets to")
END_INIT_SIM_OBJECT_PARAMS(EtherBus)
CREATE_SIM_OBJECT(EtherBus)
EtherBus *
EtherBusParams::create()
{
return new EtherBus(getInstanceName(), speed, loopback, packet_dump);
return new EtherBus(name, speed, loopback, dump);
}
REGISTER_SIM_OBJECT("EtherBus", EtherBus)

23
src/dev/etherdump.cc
View File

@@ -40,7 +40,7 @@
#include "base/misc.hh"
#include "base/output.hh"
#include "dev/etherdump.hh"
#include "sim/builder.hh"
#include "params/EtherDump.hh"
#include "sim/core.hh"
using std::string;
@@ -116,23 +116,8 @@ EtherDump::dumpPacket(EthPacketPtr &packet)
stream.flush();
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
Param<string> file;
Param<int> maxlen;
END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
INIT_PARAM(file, "file to dump packets to"),
INIT_PARAM(maxlen, "max portion of packet data to dump")
END_INIT_SIM_OBJECT_PARAMS(EtherDump)
CREATE_SIM_OBJECT(EtherDump)
EtherDump *
EtherDumpParams::create()
{
return new EtherDump(getInstanceName(), simout.resolve(file), maxlen);
return new EtherDump(name, simout.resolve(file), maxlen);
}
REGISTER_SIM_OBJECT("EtherDump", EtherDump)

4
src/dev/etherint.cc
View File

@@ -30,7 +30,6 @@
#include "dev/etherint.hh"
#include "base/misc.hh"
#include "sim/param.hh"
#include "sim/sim_object.hh"
void
@@ -42,6 +41,3 @@ EtherInt::setPeer(EtherInt *p)
peer = p;
}
DEFINE_SIM_OBJECT_CLASS_NAME("EtherInt", EtherInt)

32
src/dev/etherlink.cc
View File

@@ -44,7 +44,7 @@
#include "dev/etherint.hh"
#include "dev/etherlink.hh"
#include "dev/etherpkt.hh"
#include "sim/builder.hh"
#include "params/EtherLink.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
#include "sim/core.hh"
@@ -272,32 +272,8 @@ LinkDelayEvent::createForUnserialize(Checkpoint *cp, const string &section)
REGISTER_SERIALIZEABLE("LinkDelayEvent", LinkDelayEvent)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
SimObjectParam<EtherInt *> int1;
SimObjectParam<EtherInt *> int2;
Param<double> speed;
Param<Tick> delay;
Param<Tick> delay_var;
SimObjectParam<EtherDump *> dump;
END_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherLink)
INIT_PARAM(int1, "interface 1"),
INIT_PARAM(int2, "interface 2"),
INIT_PARAM(speed, "link speed in bits per second"),
INIT_PARAM(delay, "transmit delay of packets in us"),
INIT_PARAM(delay_var, "Difference in amount of time to traverse wire"),
INIT_PARAM(dump, "object to dump network packets to")
END_INIT_SIM_OBJECT_PARAMS(EtherLink)
CREATE_SIM_OBJECT(EtherLink)
EtherLink *
EtherLinkParams::create()
{
return new EtherLink(getInstanceName(), int1, int2, speed, delay, delay_var,
dump);
return new EtherLink(name, int1, int2, speed, delay, delay_var, dump);
}
REGISTER_SIM_OBJECT("EtherLink", EtherLink)

28
src/dev/ethertap.cc
View File

@@ -50,7 +50,7 @@
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/ethertap.hh"
#include "sim/builder.hh"
#include "params/EtherTap.hh"
using namespace std;
@@ -313,28 +313,10 @@ EtherTap::unserialize(Checkpoint *cp, const std::string &section)
//=====================================================================
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
SimObjectParam<EtherInt *> peer;
SimObjectParam<EtherDump *> dump;
Param<unsigned> port;
Param<unsigned> bufsz;
END_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherTap)
INIT_PARAM_DFLT(peer, "peer interface", NULL),
INIT_PARAM_DFLT(dump, "object to dump network packets to", NULL),
INIT_PARAM_DFLT(port, "tap port", 3500),
INIT_PARAM_DFLT(bufsz, "tap buffer size", 10000)
END_INIT_SIM_OBJECT_PARAMS(EtherTap)
CREATE_SIM_OBJECT(EtherTap)
EtherTap *
EtherTapParams::create()
{
EtherTap *tap = new EtherTap(getInstanceName(), dump, port, bufsz);
EtherTap *tap = new EtherTap(name, dump, port, bufsz);
if (peer) {
tap->setPeer(peer);
@@ -343,5 +325,3 @@ CREATE_SIM_OBJECT(EtherTap)
return tap;
}
REGISTER_SIM_OBJECT("EtherTap", EtherTap)

105
src/dev/i8254xGBe.cc
View File

@@ -40,17 +40,18 @@
* @todo really there are multiple dma engines.. we should implement them.
*/
#include <algorithm>
#include "base/inet.hh"
#include "base/trace.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/IGbE.hh"
#include "params/IGbEInt.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
#include <algorithm>
using namespace iGbReg;
using namespace Net;
@@ -1446,24 +1447,10 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
SimObjectParam<EtherInt *> peer;
SimObjectParam<IGbE *> device;
END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
INIT_PARAM_DFLT(peer, "peer interface", NULL),
INIT_PARAM(device, "Ethernet device of this interface")
END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
CREATE_SIM_OBJECT(IGbEInt)
IGbEInt *
IGbEIntParams::create()
{
IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
IGbEInt *dev_int = new IGbEInt(name, device);
EtherInt *p = (EtherInt *)peer;
if (p) {
@@ -1474,80 +1461,8 @@ CREATE_SIM_OBJECT(IGbEInt)
return dev_int;
}
REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> min_backoff_delay;
Param<Tick> max_backoff_delay;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
Param<Tick> config_latency;
Param<std::string> hardware_address;
Param<bool> use_flow_control;
Param<int> rx_fifo_size;
Param<int> tx_fifo_size;
Param<int> rx_desc_cache_size;
Param<int> tx_desc_cache_size;
Param<Tick> clock;
END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
INIT_PARAM(clock,"Clock rate for the device to tick at")
END_INIT_SIM_OBJECT_PARAMS(IGbE)
CREATE_SIM_OBJECT(IGbE)
IGbE *
IGbEParams::create()
{
IGbE::Params *params = new IGbE::Params;
params->name = getInstanceName();
params->platform = platform;
params->system = system;
params->min_backoff_delay = min_backoff_delay;
params->max_backoff_delay = max_backoff_delay;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->hardware_address = hardware_address;
params->use_flow_control = use_flow_control;
params->rx_fifo_size = rx_fifo_size;
params->tx_fifo_size = tx_fifo_size;
params->rx_desc_cache_size = rx_desc_cache_size;
params->tx_desc_cache_size = tx_desc_cache_size;
params->clock = clock;
return new IGbE(params);
return new IGbE(this);
}
REGISTER_SIM_OBJECT("IGbE", IGbE)

21
src/dev/i8254xGBe.hh
View File

@@ -45,6 +45,7 @@
#include "dev/i8254xGBe_defs.hh"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
#include "params/IGbE.hh"
#include "sim/eventq.hh"
class IGbEInt;
@@ -585,19 +586,14 @@ class IGbE : public PciDev
TxDescCache txDescCache;
public:
struct Params : public PciDev::Params
typedef IGbEParams Params;
const Params *
params() const
{
Net::EthAddr hardware_address;
bool use_flow_control;
int rx_fifo_size;
int tx_fifo_size;
int rx_desc_cache_size;
int tx_desc_cache_size;
Tick clock;
};
return dynamic_cast<const Params *>(_params);
}
IGbE(Params *params);
~IGbE() {;}
~IGbE() {}
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
@@ -612,9 +608,6 @@ class IGbE : public PciDev
void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
const Params *params() const {return (const Params *)_params; }
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual unsigned int drain(Event *de);

58
src/dev/ide_ctrl.cc
View File

@@ -44,7 +44,7 @@
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/IdeController.hh"
#include "sim/sim_object.hh"
#include "sim/byteswap.hh"
@@ -745,58 +745,8 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> min_backoff_delay;
Param<Tick> max_backoff_delay;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
Param<Tick> config_latency;
SimObjectVectorParam<IdeDisk *> disks;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(disks, "IDE disks attached to this controller")
END_INIT_SIM_OBJECT_PARAMS(IdeController)
CREATE_SIM_OBJECT(IdeController)
IdeController *
IdeControllerParams::create()
{
IdeController::Params *params = new IdeController::Params;
params->name = getInstanceName();
params->platform = platform;
params->system = system;
params->min_backoff_delay = min_backoff_delay;
params->max_backoff_delay = max_backoff_delay;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->disks = disks;
return new IdeController(params);
return new IdeController(this);
}
REGISTER_SIM_OBJECT("IdeController", IdeController)
#endif //DOXYGEN_SHOULD_SKIP_THIS

9
src/dev/ide_ctrl.hh
View File

@@ -40,6 +40,7 @@
#include "dev/pcidev.hh"
#include "dev/pcireg.h"
#include "dev/io_device.hh"
#include "params/IdeController.hh"
#define BMIC0 0x0 // Bus master IDE command register
#define BMIS0 0x2 // Bus master IDE status register
@@ -193,14 +194,8 @@ class IdeController : public PciDev
bool isDiskSelected(IdeDisk *diskPtr);
public:
struct Params : public PciDev::Params
{
/** Array of disk objects */
std::vector<IdeDisk *> disks;
};
typedef IdeControllerParams Params;
const Params *params() const { return (const Params *)_params; }
public:
IdeController(Params *p);
~IdeController();

40
src/dev/ide_disk.cc
View File

@@ -38,18 +38,16 @@
#include <deque>
#include <string>
#include "arch/isa_traits.hh"
#include "base/chunk_generator.hh"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include "dev/disk_image.hh"
#include "dev/ide_disk.hh"
#include "dev/ide_ctrl.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/alpha/tsunami_pchip.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "dev/ide_disk.hh"
#include "params/IdeDisk.hh"
#include "sim/core.hh"
#include "arch/isa_traits.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace TheISA;
@@ -1116,32 +1114,8 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
enum DriveID { master, slave };
static const char *DriveID_strings[] = { "master", "slave" };
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
SimObjectParam<DiskImage *> image;
SimpleEnumParam<DriveID> driveID;
Param<int> delay;
END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
INIT_PARAM(image, "Disk image"),
INIT_ENUM_PARAM(driveID, "Drive ID (0=master 1=slave)", DriveID_strings),
INIT_PARAM_DFLT(delay, "Fixed disk delay in microseconds", 1)
END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
CREATE_SIM_OBJECT(IdeDisk)
IdeDisk *
IdeDiskParams::create()
{
return new IdeDisk(getInstanceName(), image, driveID, delay);
return new IdeDisk(name, image, driveID, delay);
}
REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
#endif //DOXYGEN_SHOULD_SKIP_THIS

20
src/dev/io_device.cc
View File

@@ -32,7 +32,6 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "dev/io_device.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@@ -55,6 +54,10 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
}
PioDevice::PioDevice(const Params *p)
: MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
{}
PioDevice::~PioDevice()
{
if (pioPort)
@@ -82,6 +85,11 @@ PioDevice::drain(Event *de)
return count;
}
BasicPioDevice::BasicPioDevice(const Params *p)
: PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
pioDelay(p->pio_latency)
{}
void
BasicPioDevice::addressRanges(AddrRangeList &range_list)
{
@@ -149,7 +157,7 @@ DmaPort::recvTiming(PacketPtr pkt)
return true;
}
DmaDevice::DmaDevice(Params *p)
DmaDevice::DmaDevice(const Params *p)
: PioDevice(p), dmaPort(NULL), minBackoffDelay(p->min_backoff_delay),
maxBackoffDelay(p->max_backoff_delay)
{ }
@@ -262,8 +270,8 @@ DmaPort::sendDma()
assert(transmitList.size());
PacketPtr pkt = transmitList.front();
System::MemoryMode state = sys->getMemoryMode();
if (state == System::Timing) {
Enums::MemoryMode state = sys->getMemoryMode();
if (state == Enums::timing) {
if (backoffEvent.scheduled() || inRetry) {
DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n");
return;
@@ -290,7 +298,7 @@ DmaPort::sendDma()
backoffTime+curTick);
backoffEvent.schedule(backoffTime+curTick);
}
} else if (state == System::Atomic) {
} else if (state == Enums::atomic) {
transmitList.pop_front();
Tick lat;
@@ -330,5 +338,3 @@ DmaDevice::~DmaDevice()
if (dmaPort)
delete dmaPort;
}

67
src/dev/io_device.hh
View File

@@ -35,6 +35,9 @@
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/tport.hh"
#include "params/BasicPioDevice.hh"
#include "params/DmaDevice.hh"
#include "params/PioDevice.hh"
#include "sim/sim_object.hh"
class Event;
@@ -186,29 +189,16 @@ class PioDevice : public MemObject
virtual Tick write(PacketPtr pkt) = 0;
public:
/** Params struct which is extended through each device based on
* the parameters it needs. Since we are re-writing everything, we
* might as well start from the bottom this time. */
struct Params
{
std::string name;
Platform *platform;
System *system;
};
protected:
Params *_params;
public:
const Params *params() const { return _params; }
PioDevice(Params *p)
: MemObject(p->name), platform(p->platform), sys(p->system),
pioPort(NULL), _params(p)
{}
typedef PioDeviceParams Params;
PioDevice(const Params *p);
virtual ~PioDevice();
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual void init();
virtual unsigned int drain(Event *de);
@@ -229,13 +219,6 @@ class PioDevice : public MemObject
class BasicPioDevice : public PioDevice
{
public:
struct Params : public PioDevice::Params
{
Addr pio_addr;
Tick pio_delay;
};
protected:
/** Address that the device listens to. */
Addr pioAddr;
@@ -247,10 +230,14 @@ class BasicPioDevice : public PioDevice
Tick pioDelay;
public:
BasicPioDevice(Params *p)
: PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
pioDelay(p->pio_delay)
{}
typedef BasicPioDeviceParams Params;
BasicPioDevice(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/** return the address ranges that this device responds to.
* @param range_list range list to populate with ranges
@@ -261,22 +248,22 @@ class BasicPioDevice : public PioDevice
class DmaDevice : public PioDevice
{
public:
struct Params : public PioDevice::Params
{
Tick min_backoff_delay;
Tick max_backoff_delay;
};
protected:
DmaPort *dmaPort;
Tick minBackoffDelay;
Tick maxBackoffDelay;
public:
DmaDevice(Params *p);
typedef DmaDeviceParams Params;
DmaDevice(const Params *p);
virtual ~DmaDevice();
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
{
dmaPort->dmaAction(MemCmd::WriteInvalidateReq,

76
src/dev/isa_fake.cc
View File

@@ -36,7 +36,6 @@
#include "dev/isa_fake.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
@@ -44,13 +43,13 @@ using namespace std;
IsaFake::IsaFake(Params *p)
: BasicPioDevice(p)
{
if (!params()->retBadAddr)
if (!p->ret_bad_addr)
pioSize = p->pio_size;
retData8 = params()->retData8;
retData16 = params()->retData16;
retData32 = params()->retData32;
retData64 = params()->retData64;
retData8 = p->ret_data8;
retData16 = p->ret_data16;
retData32 = p->ret_data32;
retData64 = p->ret_data64;
}
Tick
@@ -58,10 +57,10 @@ IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
if (params()->warnAccess != "")
if (params()->warn_access != "")
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
if (params()->retBadAddr) {
if (params()->ret_bad_addr) {
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
@@ -93,7 +92,7 @@ IsaFake::read(PacketPtr pkt)
Tick
IsaFake::write(PacketPtr pkt)
{
if (params()->warnAccess != "") {
if (params()->warn_access != "") {
uint64_t data;
switch (pkt->getSize()) {
case sizeof(uint64_t):
@@ -114,7 +113,7 @@ IsaFake::write(PacketPtr pkt)
warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
name(), pkt->getAddr(), pkt->getSize(), data);
}
if (params()->retBadAddr) {
if (params()->ret_bad_addr) {
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
@@ -122,7 +121,7 @@ IsaFake::write(PacketPtr pkt)
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
if (params()->updateData) {
if (params()->update_data) {
switch (pkt->getSize()) {
case sizeof(uint64_t):
retData64 = pkt->get<uint64_t>();
@@ -145,57 +144,8 @@ IsaFake::write(PacketPtr pkt)
return pioDelay;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
Param<Addr> pio_size;
Param<bool> ret_bad_addr;
Param<bool> update_data;
Param<std::string> warn_access;
Param<uint8_t> ret_data8;
Param<uint16_t> ret_data16;
Param<uint32_t> ret_data32;
Param<uint64_t> ret_data64;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(pio_size, "Size of address range"),
INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
INIT_PARAM(update_data, "Update returned data"),
INIT_PARAM(warn_access, "Warn if this device is touched"),
INIT_PARAM(ret_data8, "Data to return if not bad addr"),
INIT_PARAM(ret_data16, "Data to return if not bad addr"),
INIT_PARAM(ret_data32, "Data to return if not bad addr"),
INIT_PARAM(ret_data64, "Data to return if not bad addr"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(IsaFake)
CREATE_SIM_OBJECT(IsaFake)
IsaFake *
IsaFakeParams::create()
{
IsaFake::Params *p = new IsaFake::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->pio_size = pio_size;
p->retBadAddr = ret_bad_addr;
p->updateData = update_data;
p->warnAccess = warn_access;
p->retData8= ret_data8;
p->retData16 = ret_data16;
p->retData32 = ret_data32;
p->retData64 = ret_data64;
p->platform = platform;
p->system = system;
return new IsaFake(p);
return new IsaFake(this);
}
REGISTER_SIM_OBJECT("IsaFake", IsaFake)

25
src/dev/isa_fake.hh
View File

@@ -35,13 +35,14 @@
#ifndef __ISA_FAKE_HH__
#define __ISA_FAKE_HH__
#include <string>
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/alpha/tsunami.hh"
#include "params/IsaFake.hh"
#include "mem/packet.hh"
#include <string>
/**
* IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
* rites. It is meant to be placed at an address range
@@ -51,27 +52,19 @@
*/
class IsaFake : public BasicPioDevice
{
public:
struct Params : public BasicPioDevice::Params
{
Addr pio_size;
bool retBadAddr;
bool updateData;
uint8_t retData8;
uint16_t retData16;
uint32_t retData32;
uint64_t retData64;
std::string warnAccess;
};
protected:
const Params *params() const { return (const Params*)_params; }
uint8_t retData8;
uint16_t retData16;
uint32_t retData32;
uint64_t retData64;
public:
typedef IsaFakeParams Params;
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/**
* The constructor for Tsunmami Fake just registers itself with the MMU.
* @param p params structure

143
src/dev/ns_gige.cc
View File

@@ -43,7 +43,8 @@
#include "dev/pciconfigall.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/NSGigE.hh"
#include "params/NSGigEInt.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
@@ -118,7 +119,7 @@ NSGigE::NSGigE(Params *p)
regsReset();
memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN);
memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);
memset(&rxDesc32, 0, sizeof(rxDesc32));
memset(&txDesc32, 0, sizeof(txDesc32));
@@ -2773,23 +2774,10 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
}
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
SimObjectParam<EtherInt *> peer;
SimObjectParam<NSGigE *> device;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
INIT_PARAM_DFLT(peer, "peer interface", NULL),
INIT_PARAM(device, "Ethernet device of this interface")
END_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
CREATE_SIM_OBJECT(NSGigEInt)
NSGigEInt *
NSGigEIntParams::create()
{
NSGigEInt *dev_int = new NSGigEInt(getInstanceName(), device);
NSGigEInt *dev_int = new NSGigEInt(name, device);
EtherInt *p = (EtherInt *)peer;
if (p) {
@@ -2800,121 +2788,8 @@ CREATE_SIM_OBJECT(NSGigEInt)
return dev_int;
}
REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> min_backoff_delay;
Param<Tick> max_backoff_delay;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
Param<Tick> config_latency;
Param<Tick> clock;
Param<bool> dma_desc_free;
Param<bool> dma_data_free;
Param<Tick> dma_read_delay;
Param<Tick> dma_write_delay;
Param<Tick> dma_read_factor;
Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
Param<Tick> intr_delay;
Param<Tick> rx_delay;
Param<Tick> tx_delay;
Param<uint32_t> rx_fifo_size;
Param<uint32_t> tx_fifo_size;
Param<bool> rx_filter;
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(clock, "State machine cycle time"),
INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
INIT_PARAM(dma_data_free, "DMA of Data is free"),
INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
INIT_PARAM(rx_delay, "Receive Delay"),
INIT_PARAM(tx_delay, "Transmit Delay"),
INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, ""),
INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(NSGigE)
CREATE_SIM_OBJECT(NSGigE)
NSGigE *
NSGigEParams::create()
{
NSGigE::Params *params = new NSGigE::Params;
params->name = getInstanceName();
params->platform = platform;
params->system = system;
params->min_backoff_delay = min_backoff_delay;
params->max_backoff_delay = max_backoff_delay;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->clock = clock;
params->dma_desc_free = dma_desc_free;
params->dma_data_free = dma_data_free;
params->dma_read_delay = dma_read_delay;
params->dma_write_delay = dma_write_delay;
params->dma_read_factor = dma_read_factor;
params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
params->pio_delay = pio_latency;
params->intr_delay = intr_delay;
params->rx_delay = rx_delay;
params->tx_delay = tx_delay;
params->rx_fifo_size = rx_fifo_size;
params->tx_fifo_size = tx_fifo_size;
params->rx_filter = rx_filter;
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
return new NSGigE(params);
return new NSGigE(this);
}
REGISTER_SIM_OBJECT("NSGigE", NSGigE)

26
src/dev/ns_gige.hh
View File

@@ -45,6 +45,7 @@
#include "dev/ns_gige_reg.h"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
#include "params/NSGigE.hh"
#include "sim/eventq.hh"
// Hash filtering constants
@@ -349,31 +350,10 @@ class NSGigE : public PciDev
NSGigEInt *interface;
public:
struct Params : public PciDev::Params
{
Tick clock;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;
bool dma_desc_free;
bool dma_data_free;
Tick dma_read_delay;
Tick dma_write_delay;
Tick dma_read_factor;
Tick dma_write_factor;
bool rx_filter;
Net::EthAddr eaddr;
uint32_t tx_fifo_size;
uint32_t rx_fifo_size;
bool rx_thread;
bool tx_thread;
bool rss;
bool dma_no_allocate;
};
typedef NSGigEParams Params;
const Params *params() const { return (const Params *)_params; }
NSGigE(Params *params);
~NSGigE();
const Params *params() const { return (const Params *)_params; }
virtual Tick writeConfig(PacketPtr pkt);

27
src/dev/pciconfigall.cc
View File

@@ -39,7 +39,7 @@
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/PciConfigAll.hh"
#include "sim/system.hh"
using namespace std;
@@ -97,27 +97,8 @@ PciConfigAll::addressRanges(AddrRangeList &range_list)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
Param<Tick> pio_latency;
Param<int> bus;
Param<Addr> size;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(bus, "Bus that this object handles config space for"),
INIT_PARAM(size, "The size of config space"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
PciConfigAll *
PciConfigAllParams::create()
{
PciConfigAll::Params *p = new PciConfigAll::Params;
p->pio_delay = pio_latency;
@@ -129,6 +110,4 @@ CREATE_SIM_OBJECT(PciConfigAll)
return new PciConfigAll(p);
}
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
#endif // DOXYGEN_SHOULD_SKIP_THIS

160
src/dev/pcidev.cc
View File

@@ -48,9 +48,8 @@
#include "dev/alpha/tsunamireg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/PciConfigData.hh"
#include "sim/byteswap.hh"
#include "sim/param.hh"
#include "sim/core.hh"
using namespace std;
@@ -84,8 +83,8 @@ PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
PciDev::PciDev(Params *p)
: DmaDevice(p), plat(p->platform), configData(p->configData),
pioDelay(p->pio_delay), configDelay(p->config_delay),
: DmaDevice(p), plat(p->platform), configData(p->configdata),
pioDelay(p->pio_latency), configDelay(p->config_latency),
configPort(NULL)
{
// copy the config data from the PciConfigData object
@@ -97,7 +96,7 @@ PciDev::PciDev(Params *p)
memset(BARAddrs, 0, sizeof(BARAddrs));
plat->registerPciDevice(0, p->deviceNum, p->functionNum,
plat->registerPciDevice(0, p->pci_dev, p->pci_func,
letoh(configData->config.interruptLine));
}
@@ -136,21 +135,21 @@ PciDev::readConfig(PacketPtr pkt)
pkt->set<uint8_t>(config.data[offset]);
DPRINTF(PCIDEV,
"readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint8_t>());
break;
case sizeof(uint16_t):
pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
DPRINTF(PCIDEV,
"readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
DPRINTF(PCIDEV,
"readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint32_t>());
break;
default:
@@ -200,7 +199,7 @@ PciDev::writeConfig(PacketPtr pkt)
}
DPRINTF(PCIDEV,
"writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint8_t>());
break;
case sizeof(uint16_t):
@@ -217,7 +216,7 @@ PciDev::writeConfig(PacketPtr pkt)
}
DPRINTF(PCIDEV,
"writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
@@ -277,7 +276,7 @@ PciDev::writeConfig(PacketPtr pkt)
}
DPRINTF(PCIDEV,
"writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint32_t>());
break;
default:
@@ -307,113 +306,38 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
Param<uint16_t> VendorID;
Param<uint16_t> DeviceID;
Param<uint16_t> Command;
Param<uint16_t> Status;
Param<uint8_t> Revision;
Param<uint8_t> ProgIF;
Param<uint8_t> SubClassCode;
Param<uint8_t> ClassCode;
Param<uint8_t> CacheLineSize;
Param<uint8_t> LatencyTimer;
Param<uint8_t> HeaderType;
Param<uint8_t> BIST;
Param<uint32_t> BAR0;
Param<uint32_t> BAR1;
Param<uint32_t> BAR2;
Param<uint32_t> BAR3;
Param<uint32_t> BAR4;
Param<uint32_t> BAR5;
Param<uint32_t> CardbusCIS;
Param<uint16_t> SubsystemVendorID;
Param<uint16_t> SubsystemID;
Param<uint32_t> ExpansionROM;
Param<uint8_t> InterruptLine;
Param<uint8_t> InterruptPin;
Param<uint8_t> MinimumGrant;
Param<uint8_t> MaximumLatency;
Param<uint32_t> BAR0Size;
Param<uint32_t> BAR1Size;
Param<uint32_t> BAR2Size;
Param<uint32_t> BAR3Size;
Param<uint32_t> BAR4Size;
Param<uint32_t> BAR5Size;
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
INIT_PARAM(VendorID, "Vendor ID"),
INIT_PARAM(DeviceID, "Device ID"),
INIT_PARAM_DFLT(Command, "Command Register", 0x00),
INIT_PARAM_DFLT(Status, "Status Register", 0x00),
INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
INIT_PARAM(SubClassCode, "Sub-Class Code"),
INIT_PARAM(ClassCode, "Class Code"),
INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
INIT_PARAM(InterruptLine, "Interrupt Line Register"),
INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
CREATE_SIM_OBJECT(PciConfigData)
PciConfigData *
PciConfigDataParams::create()
{
PciConfigData *data = new PciConfigData(getInstanceName());
PciConfigData *data = new PciConfigData(name);
data->config.vendor = htole(VendorID.returnValue());
data->config.device = htole(DeviceID.returnValue());
data->config.command = htole(Command.returnValue());
data->config.status = htole(Status.returnValue());
data->config.revision = htole(Revision.returnValue());
data->config.progIF = htole(ProgIF.returnValue());
data->config.subClassCode = htole(SubClassCode.returnValue());
data->config.classCode = htole(ClassCode.returnValue());
data->config.cacheLineSize = htole(CacheLineSize.returnValue());
data->config.latencyTimer = htole(LatencyTimer.returnValue());
data->config.headerType = htole(HeaderType.returnValue());
data->config.bist = htole(BIST.returnValue());
data->config.vendor = htole(VendorID);
data->config.device = htole(DeviceID);
data->config.command = htole(Command);
data->config.status = htole(Status);
data->config.revision = htole(Revision);
data->config.progIF = htole(ProgIF);
data->config.subClassCode = htole(SubClassCode);
data->config.classCode = htole(ClassCode);
data->config.cacheLineSize = htole(CacheLineSize);
data->config.latencyTimer = htole(LatencyTimer);
data->config.headerType = htole(HeaderType);
data->config.bist = htole(BIST);
data->config.baseAddr[0] = htole(BAR0.returnValue());
data->config.baseAddr[1] = htole(BAR1.returnValue());
data->config.baseAddr[2] = htole(BAR2.returnValue());
data->config.baseAddr[3] = htole(BAR3.returnValue());
data->config.baseAddr[4] = htole(BAR4.returnValue());
data->config.baseAddr[5] = htole(BAR5.returnValue());
data->config.cardbusCIS = htole(CardbusCIS.returnValue());
data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
data->config.subsystemID = htole(SubsystemID.returnValue());
data->config.expansionROM = htole(ExpansionROM.returnValue());
data->config.interruptLine = htole(InterruptLine.returnValue());
data->config.interruptPin = htole(InterruptPin.returnValue());
data->config.minimumGrant = htole(MinimumGrant.returnValue());
data->config.maximumLatency = htole(MaximumLatency.returnValue());
data->config.baseAddr[0] = htole(BAR0);
data->config.baseAddr[1] = htole(BAR1);
data->config.baseAddr[2] = htole(BAR2);
data->config.baseAddr[3] = htole(BAR3);
data->config.baseAddr[4] = htole(BAR4);
data->config.baseAddr[5] = htole(BAR5);
data->config.cardbusCIS = htole(CardbusCIS);
data->config.subsystemVendorID = htole(SubsystemVendorID);
data->config.subsystemID = htole(SubsystemID);
data->config.expansionROM = htole(ExpansionROM);
data->config.interruptLine = htole(InterruptLine);
data->config.interruptPin = htole(InterruptPin);
data->config.minimumGrant = htole(MinimumGrant);
data->config.maximumLatency = htole(MaximumLatency);
data->BARSize[0] = BAR0Size;
data->BARSize[1] = BAR1Size;
@@ -426,13 +350,9 @@ CREATE_SIM_OBJECT(PciConfigData)
uint32_t barsize = data->BARSize[i];
if (barsize != 0 && !isPowerOf2(barsize)) {
fatal("%s: BAR %d size %d is not a power of 2\n",
getInstanceName(), i, data->BARSize[i]);
name, i, data->BARSize[i]);
}
}
return data;
}
REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
#endif // DOXYGEN_SHOULD_SKIP_THIS

35
src/dev/pcidev.hh
View File

@@ -42,6 +42,7 @@
#include "dev/io_device.hh"
#include "dev/pcireg.h"
#include "dev/platform.hh"
#include "params/PciDevice.hh"
#include "sim/byteswap.hh"
#define BAR_IO_MASK 0x3
@@ -105,32 +106,12 @@ class PciDev : public DmaDevice
};
public:
struct Params : public DmaDevice::Params
typedef PciDeviceParams Params;
const Params *
params() const
{
/**
* A pointer to the object that contains the first 64 bytes of
* config space
*/
PciConfigData *configData;
/** The bus number we are on */
uint32_t busNum;
/** The device number we have */
uint32_t deviceNum;
/** The function number */
uint32_t functionNum;
/** The latency for pio accesses. */
Tick pio_delay;
/** The latency for a config access. */
Tick config_delay;
};
public:
const Params *params() const { return (const Params *)_params; }
return dynamic_cast<const Params *>(_params);
}
protected:
/** The current config space. Unlike the PciConfigData this is
@@ -266,8 +247,8 @@ class PciDev : public DmaDevice
if (if_name == "config") {
if (configPort != NULL)
panic("pciconfig port already connected to.");
configPort = new PciConfigPort(this, params()->busNum,
params()->deviceNum, params()->functionNum,
configPort = new PciConfigPort(this, params()->pci_bus,
params()->pci_dev, params()->pci_func,
params()->platform);
return configPort;
}

5
src/dev/platform.cc
View File

@@ -31,7 +31,6 @@
#include "base/misc.hh"
#include "dev/platform.hh"
#include "sim/builder.hh"
#include "sim/sim_exit.hh"
using namespace std;
@@ -79,7 +78,3 @@ Platform::registerPciDevice(uint8_t bus, uint8_t dev, uint8_t func, uint8_t intr
intLines.set(intr);
}
DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)

31
src/dev/simconsole.cc
View File

@@ -52,7 +52,7 @@
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "sim/builder.hh"
#include "params/SimConsole.hh"
using namespace std;
@@ -325,38 +325,17 @@ SimConsole::out(char c)
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
SimObjectParam<IntrControl *> intr_control;
Param<string> output;
Param<int> port;
Param<bool> append_name;
Param<int> number;
END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
INIT_PARAM(intr_control, "interrupt controller"),
INIT_PARAM(output, "file to dump output to"),
INIT_PARAM(port, ""),
INIT_PARAM_DFLT(append_name, "append name() to filename", true),
INIT_PARAM_DFLT(number, "console number", 0)
END_INIT_SIM_OBJECT_PARAMS(SimConsole)
CREATE_SIM_OBJECT(SimConsole)
SimConsole *
SimConsoleParams::create()
{
string filename = output;
ostream *stream = NULL;
if (!filename.empty()) {
if (append_name)
filename += "." + getInstanceName();
filename += "." + name;
stream = simout.find(filename);
}
return new SimConsole(getInstanceName(), stream, number, port);
return new SimConsole(name, stream, number, port);
}
REGISTER_SIM_OBJECT("SimConsole", SimConsole)

23
src/dev/simple_disk.cc
View File

@@ -45,7 +45,7 @@
#include "dev/disk_image.hh"
#include "dev/simple_disk.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "params/SimpleDisk.hh"
#include "sim/system.hh"
using namespace std;
@@ -91,23 +91,8 @@ SimpleDisk::write(Addr addr, baddr_t block, int count)
#endif
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
SimObjectParam<System *> system;
SimObjectParam<DiskImage *> disk;
END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(disk, "Disk Image")
END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
CREATE_SIM_OBJECT(SimpleDisk)
SimpleDisk *
SimpleDiskParams::create()
{
return new SimpleDisk(getInstanceName(), system, disk);
return new SimpleDisk(name, system, disk);
}
REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)

176
src/dev/sinic.cc
View File

@@ -32,6 +32,7 @@
#include <limits>
#include <string>
#include "arch/vtophys.hh"
#include "base/inet.hh"
#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
@@ -39,12 +40,10 @@
#include "dev/sinic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/debug.hh"
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
#include "arch/vtophys.hh"
using namespace Net;
using namespace TheISA;
@@ -754,7 +753,7 @@ Device::reset()
regs.TxFifoSize = params()->tx_fifo_size;
regs.RxFifoMark = params()->rx_fifo_threshold;
regs.TxFifoMark = params()->tx_fifo_threshold;
regs.HwAddr = params()->eaddr;
regs.HwAddr = params()->hardware_address;
rxList.clear();
rxBusy.clear();
@@ -1596,172 +1595,23 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
/* namespace Sinic */ }
BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
SimObjectParam<EtherInt *> peer;
SimObjectParam<Sinic::Device *> device;
END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
INIT_PARAM_DFLT(peer, "peer interface", NULL),
INIT_PARAM(device, "Ethernet device of this interface")
END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
CREATE_SIM_OBJECT_WNS(Sinic, SinicInterface)
Sinic::Interface *
SinicIntParams::create()
{
Sinic::Interface *dev_int = new Sinic::Interface(getInstanceName(), device);
using namespace Sinic;
EtherInt *p = (EtherInt *)peer;
if (p) {
dev_int->setPeer(p);
p->setPeer(dev_int);
Interface *dev_int = new Interface(name, device);
if (peer) {
dev_int->setPeer(peer);
peer->setPeer(dev_int);
}
return dev_int;
}
REGISTER_SIM_OBJECT_WNS(Sinic, "SinicInt", SinicInterface)
BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> min_backoff_delay;
Param<Tick> max_backoff_delay;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
Param<Tick> config_latency;
Param<Tick> intr_delay;
Param<Tick> clock;
Param<Tick> dma_read_delay;
Param<Tick> dma_read_factor;
Param<Tick> dma_write_delay;
Param<Tick> dma_write_factor;
Param<Tick> rx_delay;
Param<Tick> tx_delay;
Param<uint32_t> rx_max_copy;
Param<uint32_t> tx_max_copy;
Param<uint32_t> rx_max_intr;
Param<uint32_t> rx_fifo_size;
Param<uint32_t> tx_fifo_size;
Param<uint32_t> rx_fifo_threshold;
Param<uint32_t> rx_fifo_low_mark;
Param<uint32_t> tx_fifo_high_mark;
Param<uint32_t> tx_fifo_threshold;
Param<bool> rx_filter;
Param<std::string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
Param<uint32_t> virtual_count;
Param<bool> zero_copy;
Param<bool> delay_copy;
Param<bool> virtual_addr;
END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(clock, "State machine cycle time"),
INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(rx_delay, "Receive Delay"),
INIT_PARAM(tx_delay, "Transmit Delay"),
INIT_PARAM(rx_max_copy, "rx max copy"),
INIT_PARAM(tx_max_copy, "rx max copy"),
INIT_PARAM(rx_max_intr, "rx max intr"),
INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, ""),
INIT_PARAM(rss, ""),
INIT_PARAM(virtual_count, ""),
INIT_PARAM(zero_copy, ""),
INIT_PARAM(delay_copy, ""),
INIT_PARAM(virtual_addr, "")
END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
CREATE_SIM_OBJECT_WNS(Sinic, SinicDevice)
Sinic::Device *
SinicParams::create()
{
Sinic::Sinic::Device::Params *params = new Device::Params;
params->name = getInstanceName();
params->platform = platform;
params->system = system;
params->min_backoff_delay = min_backoff_delay;
params->max_backoff_delay = max_backoff_delay;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->intr_delay = intr_delay;
params->clock = clock;
params->dma_read_delay = dma_read_delay;
params->dma_read_factor = dma_read_factor;
params->dma_write_delay = dma_write_delay;
params->dma_write_factor = dma_write_factor;
params->tx_delay = tx_delay;
params->rx_delay = rx_delay;
params->rx_max_copy = rx_max_copy;
params->tx_max_copy = tx_max_copy;
params->rx_max_intr = rx_max_intr;
params->rx_fifo_size = rx_fifo_size;
params->tx_fifo_size = tx_fifo_size;
params->rx_fifo_threshold = rx_fifo_threshold;
params->rx_fifo_low_mark = rx_fifo_low_mark;
params->tx_fifo_high_mark = tx_fifo_high_mark;
params->tx_fifo_threshold = tx_fifo_threshold;
params->rx_filter = rx_filter;
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
params->virtual_count = virtual_count;
params->zero_copy = zero_copy;
params->delay_copy = delay_copy;
params->virtual_addr = virtual_addr;
return new Sinic::Device(params);
return new Sinic::Device(this);
}
REGISTER_SIM_OBJECT_WNS(Sinic, "Sinic", SinicDevice)

47
src/dev/sinic.hh
View File

@@ -39,6 +39,8 @@
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
#include "dev/sinicreg.hh"
#include "params/Sinic.hh"
#include "params/SinicInt.hh"
#include "sim/eventq.hh"
namespace Sinic {
@@ -80,12 +82,8 @@ class Base : public PciDev
* Construction/Destruction/Parameters
*/
public:
struct Params : public PciDev::Params
{
Tick clock;
Tick intr_delay;
};
typedef SinicParams Params;
const Params *params() const { return (const Params *)_params; }
Base(Params *p);
};
@@ -313,43 +311,8 @@ class Device : public Base
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Construction/Destruction/Parameters
*/
public:
struct Params : public Base::Params
{
Tick tx_delay;
Tick rx_delay;
bool rx_filter;
Net::EthAddr eaddr;
uint32_t rx_max_copy;
uint32_t tx_max_copy;
uint32_t rx_max_intr;
uint32_t rx_fifo_size;
uint32_t tx_fifo_size;
uint32_t rx_fifo_threshold;
uint32_t rx_fifo_low_mark;
uint32_t tx_fifo_high_mark;
uint32_t tx_fifo_threshold;
Tick dma_read_delay;
Tick dma_read_factor;
Tick dma_write_delay;
Tick dma_write_factor;
bool rx_thread;
bool tx_thread;
bool rss;
uint32_t virtual_count;
bool zero_copy;
bool delay_copy;
bool virtual_addr;
};
protected:
const Params *params() const { return (const Params *)_params; }
public:
Device(Params *params);
Device(Params *p);
~Device();
};

42
src/dev/sparc/dtod.cc
View File

@@ -37,26 +37,25 @@
#include <string>
#include <vector>
#include "base/time.hh"
#include "base/trace.hh"
#include "dev/sparc/dtod.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
DumbTOD::DumbTOD(Params *p)
DumbTOD::DumbTOD(const Params *p)
: BasicPioDevice(p)
{
struct tm tm;
struct tm tm = p->time;
char *tz;
pioSize = 0x08;
parseTime(p->init_time, &tm);
tz = getenv("TZ");
setenv("TZ", "", 1);
tzset();
@@ -104,37 +103,8 @@ DumbTOD::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(todTime);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
VectorParam<int> time;
END_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
BEGIN_INIT_SIM_OBJECT_PARAMS(DumbTOD)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(time, "")
END_INIT_SIM_OBJECT_PARAMS(DumbTOD)
CREATE_SIM_OBJECT(DumbTOD)
DumbTOD *
DumbTODParams::create()
{
DumbTOD::Params *p = new DumbTOD::Params;
p->name =getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->init_time = time;
return new DumbTOD(p);
return new DumbTOD(this);
}
REGISTER_SIM_OBJECT("DumbTOD", DumbTOD)

17
src/dev/sparc/dtod.hh
View File

@@ -40,7 +40,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "params/DumbTOD.hh"
/**
* DumbTOD simply returns some idea of time when read. Until we finish with
@@ -52,15 +52,14 @@ class DumbTOD : public BasicPioDevice
uint64_t todTime;
public:
struct Params : public BasicPioDevice::Params
{
std::vector<int> init_time;
};
protected:
const Params *params() const { return (const Params *)_params; }
typedef DumbTODParams Params;
DumbTOD(const Params *p);
public:
DumbTOD(Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

32
src/dev/sparc/iob.cc
View File

@@ -45,11 +45,10 @@
#include "dev/platform.hh"
#include "mem/port.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
Iob::Iob(Params *p)
Iob::Iob(const Params *p)
: PioDevice(p), ic(p->platform->intrctrl)
{
iobManAddr = ULL(0x9800000000);
@@ -372,31 +371,8 @@ Iob::unserialize(Checkpoint *cp, const std::string &section)
};
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob)
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(Iob)
BEGIN_INIT_SIM_OBJECT_PARAMS(Iob)
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(Iob)
CREATE_SIM_OBJECT(Iob)
Iob *
IobParams::create()
{
Iob::Params *p = new Iob::Params;
p->name = getInstanceName();
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
return new Iob(p);
return new Iob(this);
}
REGISTER_SIM_OBJECT("Iob", Iob)

21
src/dev/sparc/iob.hh
View File

@@ -39,6 +39,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/disk_image.hh"
#include "params/Iob.hh"
class IntrControl;
@@ -123,24 +124,22 @@ class Iob : public PioDevice
void readIob(PacketPtr pkt);
void readJBus(PacketPtr pkt);
public:
struct Params : public PioDevice::Params
typedef IobParams Params;
Iob(const Params *p);
const Params *
params() const
{
Tick pio_delay;
};
protected:
const Params *params() const { return (const Params*)_params; }
public:
Iob(Params *p);
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void generateIpi(Type type, int cpu_id, int vector);
void receiveDeviceInterrupt(DeviceId devid);
bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1);
bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
uint64_t d1);
void addressRanges(AddrRangeList &range_list);

40
src/dev/sparc/mm_disk.cc
View File

@@ -40,11 +40,10 @@
#include "dev/platform.hh"
#include "mem/port.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
MmDisk::MmDisk(Params *p)
MmDisk::MmDisk(const Params *p)
: BasicPioDevice(p), image(p->image), curSector((off_t)-1), dirty(false)
{
std::memset(&diskData, 0, SectorSize);
@@ -173,39 +172,8 @@ MmDisk::serialize(std::ostream &os)
}
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
Param<Addr> pio_size;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
SimObjectParam<DiskImage *> image;
END_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
BEGIN_INIT_SIM_OBJECT_PARAMS(MmDisk)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(pio_size, "Size of address range"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(image, "disk image")
END_INIT_SIM_OBJECT_PARAMS(MmDisk)
CREATE_SIM_OBJECT(MmDisk)
MmDisk *
MmDiskParams::create()
{
MmDisk::Params *p = new MmDisk::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->image = image;
return new MmDisk(p);
return new MmDisk(this);
}
REGISTER_SIM_OBJECT("MmDisk", MmDisk)

16
src/dev/sparc/mm_disk.hh
View File

@@ -39,6 +39,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/disk_image.hh"
#include "params/MmDisk.hh"
class MmDisk : public BasicPioDevice
{
@@ -49,15 +50,14 @@ class MmDisk : public BasicPioDevice
uint8_t diskData[SectorSize];
public:
struct Params : public BasicPioDevice::Params
{
DiskImage *image;
};
protected:
const Params *params() const { return (const Params*)_params; }
typedef MmDiskParams Params;
MmDisk(const Params *p);
public:
MmDisk(Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

23
src/dev/sparc/t1000.cc
View File

@@ -39,7 +39,7 @@
#include "cpu/intr_control.hh"
#include "dev/simconsole.hh"
#include "dev/sparc/t1000.hh"
#include "sim/builder.hh"
#include "params/T1000.hh"
#include "sim/system.hh"
using namespace std;
@@ -101,23 +101,8 @@ T1000::calcConfigAddr(int bus, int dev, int func)
M5_DUMMY_RETURN
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
SimObjectParam<System *> system;
SimObjectParam<IntrControl *> intrctrl;
END_DECLARE_SIM_OBJECT_PARAMS(T1000)
BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
INIT_PARAM(system, "system"),
INIT_PARAM(intrctrl, "interrupt controller")
END_INIT_SIM_OBJECT_PARAMS(T1000)
CREATE_SIM_OBJECT(T1000)
T1000 *
T1000Params::create()
{
return new T1000(getInstanceName(), system, intrctrl);
return new T1000(name, system, intrctrl);
}
REGISTER_SIM_OBJECT("T1000", T1000)

9
src/dev/uart.cc
View File

@@ -35,19 +35,14 @@
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "dev/platform.hh"
#include "sim/builder.hh"
using namespace std;
Uart::Uart(Params *p)
: BasicPioDevice(p), platform(p->platform), cons(p->cons)
Uart::Uart(const Params *p)
: BasicPioDevice(p), platform(p->platform), cons(p->sim_console)
{
status = 0;
// set back pointers
cons->uart = this;
}
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)

19
src/dev/uart.hh
View File

@@ -37,6 +37,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "params/Uart.hh"
class SimConsole;
class Platform;
@@ -44,7 +45,6 @@ class Platform;
const int RX_INT = 0x1;
const int TX_INT = 0x2;
class Uart : public BasicPioDevice
{
@@ -54,28 +54,25 @@ class Uart : public BasicPioDevice
SimConsole *cons;
public:
struct Params : public BasicPioDevice::Params
{
SimConsole *cons;
};
typedef UartParams Params;
Uart(const Params *p);
Uart(Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/**
* Inform the uart that there is data available.
*/
virtual void dataAvailable() = 0;
/**
* Return if we have an interrupt pending
* @return interrupt status
*/
bool intStatus() { return status ? true : false; }
protected:
const Params *params() const {return (const Params *)_params; }
};
#endif // __UART_HH__

39
src/dev/uart8250.cc
View File

@@ -43,7 +43,6 @@
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
using namespace std;
using namespace TheISA;
@@ -100,12 +99,11 @@ Uart8250::IntrEvent::scheduleIntr()
}
Uart8250::Uart8250(Params *p)
Uart8250::Uart8250(const Params *p)
: Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
{
pioSize = 8;
}
Tick
@@ -338,37 +336,8 @@ Uart8250::unserialize(Checkpoint *cp, const std::string &section)
txIntrEvent.schedule(txintrwhen);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<SimConsole *> sim_console;
SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
INIT_PARAM(platform, "platform"),
INIT_PARAM(sim_console, "The Simulator Console"),
INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(Uart8250)
CREATE_SIM_OBJECT(Uart8250)
Uart8250 *
Uart8250Params::create()
{
Uart8250::Params *p = new Uart8250::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->cons = sim_console;
p->system = system;
return new Uart8250(p);
return new Uart8250(this);
}
REGISTER_SIM_OBJECT("Uart8250", Uart8250)

13
src/dev/uart8250.hh
View File

@@ -38,7 +38,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
#include "params/Uart8250.hh"
/* UART8250 Interrupt ID Register
* bit 0 Interrupt Pending 0 = true, 1 = false
@@ -70,8 +70,6 @@ class Platform;
class Uart8250 : public Uart
{
protected:
uint8_t IER, DLAB, LCR, MCR;
Tick lastTxInt;
@@ -92,13 +90,18 @@ class Uart8250 : public Uart
IntrEvent rxIntrEvent;
public:
Uart8250(Params *p);
typedef Uart8250Params Params;
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
Uart8250(const Params *p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
virtual void addressRanges(AddrRangeList &range_list);
/**
* Inform the uart that there is data available.
*/