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Major changes to how SimObjects are created and initialized. Almost all

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creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
This commit is contained in:
Nathan Binkert
2007-07-23 21:51:38 -07:00
parent 552097b92e
commit abc76f20cb
136 changed files with 2044 additions and 6740 deletions
Download Patch File Download Diff File Expand all files Collapse all files

85
src/cpu/simple/atomic.cc
View File

@@ -36,7 +36,7 @@
#include "cpu/simple/atomic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/AtomicSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
@@ -198,7 +198,7 @@ void
AtomicSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
assert(system->getMemoryMode() == System::Atomic);
assert(system->getMemoryMode() == Enums::atomic);
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
@@ -570,79 +570,11 @@ AtomicSimpleCPU::tick()
//
// AtomicSimpleCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
SimObjectParam<System *> system;
Param<int> cpu_id;
#if FULL_SYSTEM
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
Param<int> clock;
Param<int> phase;
Param<bool> defer_registration;
Param<int> width;
Param<bool> function_trace;
Param<Tick> function_trace_start;
Param<bool> simulate_stalls;
END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
INIT_PARAM(max_insts_any_thread,
"terminate when any thread reaches this inst count"),
INIT_PARAM(max_insts_all_threads,
"terminate when all threads have reached this inst count"),
INIT_PARAM(max_loads_any_thread,
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(width, "cpu width"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace"),
INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
CREATE_SIM_OBJECT(AtomicSimpleCPU)
AtomicSimpleCPU *
AtomicSimpleCPUParams::create()
{
AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -667,12 +599,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
params->process = workload;
if (workload.size() != 1)
panic("only one workload allowed");
params->process = workload[0];
#endif
AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
return cpu;
}
REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)

1
src/cpu/simple/base.cc
View File

@@ -47,7 +47,6 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
#include "sim/host.hh"

85
src/cpu/simple/timing.cc
View File

@@ -35,7 +35,7 @@
#include "cpu/simple/timing.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/TimingSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
@@ -158,7 +158,7 @@ void
TimingSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
assert(system->getMemoryMode() == System::Timing);
assert(system->getMemoryMode() == Enums::timing);
// Delete the old event if it existed.
if (fetchEvent) {
@@ -701,79 +701,11 @@ TimingSimpleCPU::DcachePort::recvRetry()
//
// TimingSimpleCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
SimObjectParam<System *> system;
Param<int> cpu_id;
#if FULL_SYSTEM
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
Param<int> clock;
Param<int> phase;
Param<bool> defer_registration;
Param<int> width;
Param<bool> function_trace;
Param<Tick> function_trace_start;
Param<bool> simulate_stalls;
END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
INIT_PARAM(max_insts_any_thread,
"terminate when any thread reaches this inst count"),
INIT_PARAM(max_insts_all_threads,
"terminate when all threads have reached this inst count"),
INIT_PARAM(max_loads_any_thread,
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(width, "cpu width"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace"),
INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
CREATE_SIM_OBJECT(TimingSimpleCPU)
TimingSimpleCPU *
TimingSimpleCPUParams::create()
{
TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -796,12 +728,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
params->process = workload;
if (workload.size() != 1)
panic("only one workload allowed");
params->process = workload[0];
#endif
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
return cpu;
}
REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)