MEM: Explicit ports and Python binding on CopyEngine

The copy-engine ports were previously created implicitly and bound
based on the dma port peer rather than relying on the normal Python
binding (connectPorts) being called explicitly. This patch makes the
copy engine port similar to all other ports in that they are visibly
in the Python class and bound using the normal explicit calls through
Python.

src/dev/CopyEngine.py

@@ -33,6 +33,7 @@ from Pci import PciDevice
 
 class CopyEngine(PciDevice):
     type = 'CopyEngine'
+    dma = VectorMasterPort("Copy engine DMA port")
     VendorID = 0x8086
     DeviceID = 0x1a38
     Revision = 0xA2 # CM2 stepping (newest listed)