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imported patch pagewalker.patch

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--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
This commit is contained in:
Gabe Black
2007-11-21 00:04:15 -08:00
parent ce26c3ccec
commit ab598eadbf
2 changed files with 6 additions and 2 deletions
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6
src/cpu/BaseCPU.py
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@@ -101,6 +101,8 @@ class BaseCPU(SimObject):
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
_mem_ports = []
if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
_mem_ports = ["itb.walker.port", "dtb.walker.port"]
def connectMemPorts(self, bus):
for p in self._mem_ports:
@@ -108,12 +110,14 @@ class BaseCPU(SimObject):
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
assert(len(self._mem_ports) < 6)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)