mem-ruby: Sequencer can be used without cache

Moved the dcache check to the LLSC functions that use it.
This allows a Sequencer to be coupled with a gem5 object
that does not need a cache (as long as it doesn't issue
LLSC instructions).

Also, icache was not used at all so it was removed.

Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31267
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/mem/ruby/system/Sequencer.cc

@@ -73,7 +73,6 @@ Sequencer::Sequencer(const Params *p)
 {
     m_outstanding_count = 0;
 
-    m_instCache_ptr = p->icache;
     m_dataCache_ptr = p->dcache;
     m_max_outstanding_requests = p->max_outstanding_requests;
     m_deadlock_threshold = p->deadlock_threshold;
@@ -81,8 +80,6 @@ Sequencer::Sequencer(const Params *p)
     m_coreId = p->coreid; // for tracking the two CorePair sequencers
     assert(m_max_outstanding_requests > 0);
     assert(m_deadlock_threshold > 0);
-    assert(m_instCache_ptr != NULL);
-    assert(m_dataCache_ptr != NULL);
 
     m_runningGarnetStandalone = p->garnet_standalone;
 }
@@ -94,6 +91,8 @@ Sequencer::~Sequencer()
 void
 Sequencer::llscLoadLinked(const Addr claddr)
 {
+    fatal_if(m_dataCache_ptr == NULL,
+        "%s must have a dcache object to support LLSC requests.", name());
     AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
     if (line) {
         line->setLocked(m_version);
@@ -105,6 +104,9 @@ Sequencer::llscLoadLinked(const Addr claddr)
 void
 Sequencer::llscClearMonitor(const Addr claddr)
 {
+    // clear monitor is called for all stores and evictions
+    if (m_dataCache_ptr == NULL)
+        return;
     AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
     if (line && line->isLocked(m_version)) {
         line->clearLocked();
@@ -116,6 +118,8 @@ Sequencer::llscClearMonitor(const Addr claddr)
 bool
 Sequencer::llscStoreConditional(const Addr claddr)
 {
+    fatal_if(m_dataCache_ptr == NULL,
+        "%s must have a dcache object to support LLSC requests.", name());
     AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
     if (!line)
         return false;
@@ -137,6 +141,7 @@ Sequencer::llscStoreConditional(const Addr claddr)
 bool
 Sequencer::llscCheckMonitor(const Addr address)
 {
+    assert(m_dataCache_ptr != NULL);
     const Addr claddr = makeLineAddress(address);
     AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
     if (!line)

src/mem/ruby/system/Sequencer.hh

@@ -212,7 +212,6 @@ class Sequencer : public RubyPort
     int m_max_outstanding_requests;
 
     CacheMemory* m_dataCache_ptr;
-    CacheMemory* m_instCache_ptr;
 
     // The cache access latency for top-level caches (L0/L1). These are
     // currently assessed at the beginning of each memory access through the

src/mem/ruby/system/Sequencer.py

@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2009 Advanced Micro Devices, Inc.
 # Copyright (c) 2020 ARM Limited
 # All rights reserved.
@@ -76,7 +88,6 @@ class RubySequencer(RubyPort):
    cxx_class = 'Sequencer'
    cxx_header = "mem/ruby/system/Sequencer.hh"
 
-   icache = Param.RubyCache("")
    dcache = Param.RubyCache("")
 
    max_outstanding_requests = Param.Int(16,