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mem-ruby: Sequencer can be used without cache

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Moved the dcache check to the LLSC functions that use it.
This allows a Sequencer to be coupled with a gem5 object
that does not need a cache (as long as it doesn't issue
LLSC instructions).

Also, icache was not used at all so it was removed.

Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31267
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2020-05-28 16:16:20 -05:00
parent aa8bca47f4
commit ab309b9e4e
19 changed files with 26 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
configs/ruby/AMD_Base_Constructor.py
View File

@@ -78,7 +78,6 @@ class CPCntrl(AMD_Base_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
self.sequencer.ruby_system = ruby_system
self.sequencer.coreid = 0
@@ -86,7 +85,6 @@ class CPCntrl(AMD_Base_Controller, CntrlBase):
self.sequencer1 = RubySequencer()
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1

6
configs/ruby/GPU_RfO.py
View File

@@ -118,7 +118,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
self.sequencer.ruby_system = ruby_system
self.sequencer.coreid = 0
@@ -126,7 +125,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer1 = RubySequencer()
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
@@ -180,7 +178,6 @@ class TCPCntrl(TCP_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.is_cpu_sequencer = True
@@ -209,7 +206,6 @@ class TCPCntrl(TCP_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.is_cpu_sequencer = True
@@ -243,7 +239,6 @@ class SQCCntrl(SQC_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.support_data_reqs = False
@@ -268,7 +263,6 @@ class SQCCntrl(SQC_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.support_data_reqs = False

5
configs/ruby/GPU_VIPER.py
View File

@@ -105,7 +105,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
self.sequencer.ruby_system = ruby_system
self.sequencer.coreid = 0
@@ -113,7 +112,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer1 = RubySequencer()
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
@@ -166,7 +164,6 @@ class TCPCntrl(TCP_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.is_cpu_sequencer = True
@@ -197,7 +194,6 @@ class TCPCntrl(TCP_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.is_cpu_sequencer = True
@@ -232,7 +228,6 @@ class SQCCntrl(SQC_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.support_data_reqs = False

4
configs/ruby/GPU_VIPER_Baseline.py
View File

@@ -104,7 +104,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
self.sequencer.ruby_system = ruby_system
self.sequencer.coreid = 0
@@ -112,7 +111,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer1 = RubySequencer()
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
@@ -165,7 +163,6 @@ class TCPCntrl(TCP_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.is_cpu_sequencer = True
@@ -196,7 +193,6 @@ class SQCCntrl(SQC_Controller, CntrlBase):
self.L1cache.resourceStalls = False
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.support_data_reqs = False

4
configs/ruby/GPU_VIPER_Region.py
View File

@@ -105,7 +105,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
self.sequencer.ruby_system = ruby_system
self.sequencer.coreid = 0
@@ -113,7 +112,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer1 = RubySequencer()
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
@@ -166,7 +164,6 @@ class TCPCntrl(TCP_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.is_cpu_sequencer = True
@@ -197,7 +194,6 @@ class SQCCntrl(SQC_Controller, CntrlBase):
self.L1cache.resourceStalls = False
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1cache
self.sequencer.dcache = self.L1cache
self.sequencer.ruby_system = ruby_system
self.sequencer.support_data_reqs = False

3
configs/ruby/Garnet_standalone.py
View File

@@ -79,8 +79,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
cacheMemory = cache,
ruby_system = ruby_system)
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
cpu_seq = RubySequencer(dcache = cache,
garnet_standalone = True,
ruby_system = ruby_system)

1
configs/ruby/MESI_Three_Level.py
View File

@@ -141,7 +141,6 @@ def create_system(options, full_system, system, dma_ports, bootmem,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j,
icache = l0i_cache,
clk_domain = clk_domain,
dcache = l0d_cache,
ruby_system = ruby_system)

2
configs/ruby/MESI_Two_Level.py
View File

@@ -102,7 +102,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
transitions_per_cycle = options.ports,
enable_prefetch = False)
cpu_seq = RubySequencer(version = i, icache = l1i_cache,
cpu_seq = RubySequencer(version = i,
dcache = l1d_cache, clk_domain = clk_domain,
ruby_system = ruby_system)

2
configs/ruby/MI_example.py
View File

@@ -92,7 +92,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
clk_domain=clk_domain,
ruby_system=ruby_system)
cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
cpu_seq = RubySequencer(version=i, dcache=cache,
clk_domain=clk_domain, ruby_system=ruby_system)
l1_cntrl.sequencer = cpu_seq

2
configs/ruby/MOESI_AMD_Base.py
View File

@@ -101,7 +101,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
self.sequencer.ruby_system = ruby_system
self.sequencer.coreid = 0
@@ -109,7 +108,6 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer1 = RubySequencer()
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1

2
configs/ruby/MOESI_CMP_directory.py
View File

@@ -113,7 +113,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
clk_domain=clk_domain,
ruby_system=ruby_system)
cpu_seq = RubySequencer(version=i, icache=l1i_cache,
cpu_seq = RubySequencer(version=i,
dcache=l1d_cache, clk_domain=clk_domain,
ruby_system=ruby_system)

2
configs/ruby/MOESI_CMP_token.py
View File

@@ -117,7 +117,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
clk_domain=clk_domain,
ruby_system=ruby_system)
cpu_seq = RubySequencer(version=i, icache=l1i_cache,
cpu_seq = RubySequencer(version=i,
dcache=l1d_cache, clk_domain=clk_domain,
ruby_system=ruby_system)

2
configs/ruby/MOESI_hammer.py
View File

@@ -109,7 +109,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
clk_domain=clk_domain,
ruby_system=ruby_system)
cpu_seq = RubySequencer(version=i, icache=l1i_cache,
cpu_seq = RubySequencer(version=i,
dcache=l1d_cache,clk_domain=clk_domain,
ruby_system=ruby_system)