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revert 5af8f40d8f2c

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This commit is contained in:
Nilay Vaish
2015-07-28 01:58:04 -05:00
parent 608641e23c
commit aafa5c3f86
55 changed files with 78 additions and 876 deletions
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20
src/cpu/simple/base.hh
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@@ -87,7 +87,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
typedef TheISA::VectorReg VectorReg;
BPredUnit *branchPred;
@@ -240,10 +239,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
Stats::Scalar numCCRegReads;
Stats::Scalar numCCRegWrites;
//number of vector register file accesses
Stats::Scalar numVectorRegReads;
Stats::Scalar numVectorRegWrites;
// number of simulated memory references
Stats::Scalar numMemRefs;
Stats::Scalar numLoadInsts;
@@ -330,13 +325,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
return thread->readCCReg(reg_idx);
}
const VectorReg &readVectorRegOperand(const StaticInst *si, int idx)
{
numVectorRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::Vector_Reg_Base;
return thread->readVectorReg(reg_idx);
}
void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
numIntRegWrites++;
@@ -365,14 +353,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
thread->setCCReg(reg_idx, val);
}
void setVectorRegOperand(const StaticInst *si, int idx,
const VectorReg &val)
{
numVectorRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::Vector_Reg_Base;
thread->setVectorReg(reg_idx, val);
}
bool readPredicate() { return thread->readPredicate(); }
void setPredicate(bool val)
{