revert 5af8f40d8f2c
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@@ -189,10 +189,6 @@ class O3ThreadContext : public ThreadContext
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return readCCRegFlat(flattenCCIndex(reg_idx));
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}
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virtual const VectorReg &readVectorReg(int reg_idx) {
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return readVectorRegFlat(flattenVectorIndex(reg_idx));
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}
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/** Sets an integer register to a value. */
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virtual void setIntReg(int reg_idx, uint64_t val) {
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setIntRegFlat(flattenIntIndex(reg_idx), val);
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@@ -210,10 +206,6 @@ class O3ThreadContext : public ThreadContext
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setCCRegFlat(flattenCCIndex(reg_idx), val);
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}
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virtual void setVectorReg(int reg_idx, const VectorReg &val) {
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setVectorRegFlat(flattenVectorIndex(reg_idx), val);
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}
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/** Reads this thread's PC state. */
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virtual TheISA::PCState pcState()
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{ return cpu->pcState(thread->threadId()); }
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@@ -254,7 +246,6 @@ class O3ThreadContext : public ThreadContext
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virtual int flattenIntIndex(int reg);
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virtual int flattenFloatIndex(int reg);
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virtual int flattenCCIndex(int reg);
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virtual int flattenVectorIndex(int reg);
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virtual int flattenMiscIndex(int reg);
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/** Returns the number of consecutive store conditional failures. */
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@@ -300,9 +291,6 @@ class O3ThreadContext : public ThreadContext
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virtual CCReg readCCRegFlat(int idx);
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virtual void setCCRegFlat(int idx, CCReg val);
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virtual const VectorReg &readVectorRegFlat(int idx);
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virtual void setVectorRegFlat(int idx, const VectorReg &val);
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};
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#endif
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