revert 5af8f40d8f2c

This commit is contained in:
Nilay Vaish
2015-07-28 01:58:04 -05:00
parent 608641e23c
commit aafa5c3f86
55 changed files with 78 additions and 876 deletions

View File

@@ -184,13 +184,6 @@ namespace MipsISA
return reg;
}
// dummy
int
flattenVectorIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg) const
{

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@@ -55,7 +55,6 @@ const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
const int NumCCRegs = 0;
const int NumVectorRegs = 0;
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
@@ -279,8 +278,7 @@ const int NumMiscRegs = MISCREG_NUMREGS;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs;
const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
@@ -299,12 +297,6 @@ typedef uint64_t MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
// vector register file entry type
typedef uint64_t VectorRegElement;
const int NumVectorRegElements = 0;
const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
typedef union {
IntReg intreg;
FloatReg fpreg;

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@@ -252,9 +252,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
// Copy vector registers when vector registers put to use.
assert(NumVectorRegs == 0);
// Copy misc. registers
for (int i = 0; i < NumMiscRegs; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));