revert 5af8f40d8f2c
This commit is contained in:
Nilay Vaish
@@ -515,9 +515,6 @@ class Operand(object):
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def isCCReg(self):
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return 0
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def isVectorReg(self):
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return 0
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def isControlReg(self):
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return 0
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@@ -754,106 +751,6 @@ class CCRegOperand(Operand):
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return wb
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class VectorRegOperand(Operand):
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def isReg(self):
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return 1
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def isVectorReg(self):
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return 1
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def __init__(self, parser, full_name, ext, is_src, is_dest):
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## Vector registers are always treated as source registers since
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## not the whole of them might be written, in which case we need
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## to retain the earlier value.
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super(VectorRegOperand, self).__init__(parser, full_name, ext,
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True, is_dest)
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self.size = 0
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def finalize(self, predRead, predWrite):
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self.flags = self.getFlags()
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self.constructor = self.makeConstructor(predRead, predWrite)
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self.op_decl = self.makeDecl()
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if self.is_src:
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self.op_rd = self.makeRead(predRead)
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self.op_src_decl = self.makeDecl()
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else:
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self.op_rd = ''
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self.op_src_decl = ''
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if self.is_dest:
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self.op_wb = self.makeWrite(predWrite)
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self.op_dest_decl = self.makeDecl()
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else:
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self.op_wb = ''
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self.op_dest_decl = ''
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def makeConstructor(self, predRead, predWrite):
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c_src = ''
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c_dest = ''
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if self.is_src:
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c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + Vector_Reg_Base;' % \
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(self.reg_spec)
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if self.hasReadPred():
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c_src = '\n\tif (%s) {%s\n\t}' % \
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(self.read_predicate, c_src)
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if self.is_dest:
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c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s + Vector_Reg_Base;' % \
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(self.reg_spec)
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c_dest += '\n\t_numVectorDestRegs++;'
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if self.hasWritePred():
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c_dest = '\n\tif (%s) {%s\n\t}' % \
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(self.write_predicate, c_dest)
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return c_src + c_dest
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def makeRead(self, predRead):
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if self.read_code != None:
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return self.buildReadCode('readVectorRegOperand')
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vector_reg_val = ''
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if predRead:
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vector_reg_val = 'xc->readVectorRegOperand(this, _sourceIndex++)'
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if self.hasReadPred():
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vector_reg_val = '(%s) ? %s : 0' % \
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(self.read_predicate, vector_reg_val)
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else:
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vector_reg_val = 'xc->readVectorRegOperand(this, %d)' % \
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self.src_reg_idx
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return '%s = %s;\n' % (self.base_name, vector_reg_val)
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def makeWrite(self, predWrite):
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if self.write_code != None:
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return self.buildWriteCode('setVectorRegOperand')
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if predWrite:
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wp = 'true'
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if self.hasWritePred():
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wp = self.write_predicate
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wcond = 'if (%s)' % (wp)
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windex = '_destIndex++'
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else:
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wcond = ''
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windex = '%d' % self.dest_reg_idx
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wb = '''
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%s
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{
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TheISA::VectorReg final_val = %s;
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xc->setVectorRegOperand(this, %s, final_val);\n
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if (traceData) { traceData->setData(final_val); }
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}''' % (wcond, self.base_name, windex)
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return wb
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def makeDecl(self):
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ctype = 'TheISA::VectorReg'
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return '%s %s;\n' % (ctype, self.base_name)
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class ControlRegOperand(Operand):
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def isReg(self):
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return 1
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@@ -921,10 +818,7 @@ class MemOperand(Operand):
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# Note that initializations in the declarations are solely
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# to avoid 'uninitialized variable' errors from the compiler.
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# Declare memory data variable.
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if 'IsVector' in self.flags:
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return 'TheISA::VectorReg %s;\n' % self.base_name
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else:
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return '%s %s = 0;\n' % (self.ctype, self.base_name)
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return '%s %s = 0;\n' % (self.ctype, self.base_name)
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def makeRead(self, predRead):
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if self.read_code != None:
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@@ -1015,7 +909,6 @@ class OperandList(object):
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self.numFPDestRegs = 0
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self.numIntDestRegs = 0
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self.numCCDestRegs = 0
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self.numVectorDestRegs = 0
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self.numMiscDestRegs = 0
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self.memOperand = None
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@@ -1038,8 +931,6 @@ class OperandList(object):
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self.numIntDestRegs += 1
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elif op_desc.isCCReg():
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self.numCCDestRegs += 1
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elif op_desc.isVectorReg():
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self.numVectorDestRegs += 1
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elif op_desc.isControlReg():
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self.numMiscDestRegs += 1
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elif op_desc.isMem():
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@@ -1236,7 +1127,6 @@ class InstObjParams(object):
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header += '\n\t_numFPDestRegs = 0;'
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header += '\n\t_numIntDestRegs = 0;'
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header += '\n\t_numCCDestRegs = 0;'
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header += '\n\t_numVectorDestRegs = 0;'
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self.constructor = header + \
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self.operands.concatAttrStrings('constructor')
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@@ -2402,8 +2292,7 @@ StaticInstPtr
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operandsREString = r'''
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(?<!\w) # neg. lookbehind assertion: prevent partial matches
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((%s)(?:_(%s))?(?:\[\w+\])?) # match: operand with optional '_'
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# then suffix, and then an optional array index.
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((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
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(?!\w) # neg. lookahead assertion: prevent partial matches
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''' % (string.join(operands, '|'), string.join(extensions, '|'))
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