diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index bdb6f25450..676559f61a 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1543,6 +1543,12 @@ SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
         (hcr.tge || mdcr.tde);
 }
 
+ExceptionClass
+SoftwareBreakpoint::ec(ThreadContext *tc) const
+{
+    return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec;
+}
+
 void
 ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
     DPRINTF(Faults, "Invoking ArmSev Fault\n");
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 132c07cae7..90b5501984 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -573,6 +573,7 @@ class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
     SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
 
     bool routeToHyp(ThreadContext *tc) const override;
+    ExceptionClass ec(ThreadContext *tc) const override;
 };
 
 // A fault that flushes the pipe, excluding the faulting instructions
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index d4e6ec0dbe..84887a1ca9 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -623,6 +623,7 @@ namespace ArmISA
         EC_FP_EXCEPTION_64         = 0x2C,
         EC_SERROR                  = 0x2F,
         EC_SOFTWARE_BREAKPOINT     = 0x38,
+        EC_SOFTWARE_BREAKPOINT_64  = 0x3C,
     };
 
     /**