From a903ff43f2cfd983d95e0ac21a3025928d8f6a52 Mon Sep 17 00:00:00 2001 From: Harshil Patel <91860903+Harshil2107@users.noreply.github.com> Date: Tue, 8 Aug 2023 09:40:07 -0700 Subject: [PATCH] tests: Add checkpoint tests for all ISAs Added save and restore checkpoint tests for arm-hello, x86-hello, x86-fs, power-hello Added mips and sparc test but mips does not support checkpoint and there is a bug in sparc. Added test file to run the tests. Change-Id: I2d3b96f95ee08aae921de9a885ac5be77d49f326 --- .../arm-hello-restore-checkpoint.py | 80 ++++++ .../arm-hello-save-checkpoint.py | 77 +++++ .../mips-hello-restore-checkpoint.py | 72 +++++ .../mips-hello-save-checkpoint.py | 89 ++++++ .../power-hello-restore-checkpoint.py | 72 +++++ .../power-hello-save-checkpoint.py | 83 ++++++ .../sparc-hello-restore-checkpoint.py | 72 +++++ .../sparc-hello-save-checkpoint.py | 80 ++++++ .../gem5/checkpoint-tests/test-checkpoints.py | 266 ++++++++++++++++++ .../x86-fs-restore-checkpoint.py | 88 ++++++ .../x86-fs-save-checkpoint.py | 101 +++++++ .../x86-hello-restore-checkpoint.py | 72 +++++ .../x86-hello-save-checkpoint.py | 83 ++++++ 13 files changed, 1235 insertions(+) create mode 100644 tests/gem5/checkpoint-tests/arm-hello-restore-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/arm-hello-save-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/mips-hello-restore-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/mips-hello-save-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/power-hello-restore-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/power-hello-save-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/sparc-hello-restore-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/sparc-hello-save-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/test-checkpoints.py create mode 100644 tests/gem5/checkpoint-tests/x86-fs-restore-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/x86-fs-save-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/x86-hello-restore-checkpoint.py create mode 100644 tests/gem5/checkpoint-tests/x86-hello-save-checkpoint.py diff --git a/tests/gem5/checkpoint-tests/arm-hello-restore-checkpoint.py b/tests/gem5/checkpoint-tests/arm-hello-restore-checkpoint.py new file mode 100644 index 0000000000..2076c8965e --- /dev/null +++ b/tests/gem5/checkpoint-tests/arm-hello-restore-checkpoint.py @@ -0,0 +1,80 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +tests/gem5/checkpoint-tests/arm-hello-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of "arm-hello64-static" binary simulation. +This configuration serves as a test of restoring a checkpoint with ARM ISA. +""" + +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource, CheckpointResource + +from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( + PrivateL1PrivateL2CacheHierarchy, +) +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + + +requires(isa_required=ISA.ARM) + +cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( + l1d_size="16kB", l1i_size="16kB", l2_size="256kB" +) + +memory = SingleChannelDDR3_1600(size="32MB") + +processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2) + +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) + +board.set_se_binary_workload( + obtain_resource("arm-hello64-static"), + checkpoint=obtain_resource("arm-hello-test-checkpoint"), +) + +sim = Simulator(board=board, full_system=False) +sim.run() + +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/arm-hello-save-checkpoint.py b/tests/gem5/checkpoint-tests/arm-hello-save-checkpoint.py new file mode 100644 index 0000000000..d0ebf7afe0 --- /dev/null +++ b/tests/gem5/checkpoint-tests/arm-hello-save-checkpoint.py @@ -0,0 +1,77 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import argparse +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource +from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( + PrivateL1PrivateL2CacheHierarchy, +) +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + +parser = argparse.ArgumentParser() + +parser.add_argument( + "--checkpoint-path", + type=str, + required=False, + default="arm-hello-test-checkpoint/", + help="The directory to store the checkpoint.", +) + +args = parser.parse_args() +requires(isa_required=ISA.ARM) + +cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( + l1d_size="16kB", l1i_size="16kB", l2_size="256kB" +) + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2) +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload(obtain_resource("arm-hello64-static")) + +sim = Simulator(board=board, full_system=False) +max_ticks = 10**6 +sim.run(max_ticks=max_ticks) +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) +print("Taking checkpoint at", args.checkpoint_path) +sim.save_checkpoint(args.checkpoint_path) +print("Done taking checkpoint") diff --git a/tests/gem5/checkpoint-tests/mips-hello-restore-checkpoint.py b/tests/gem5/checkpoint-tests/mips-hello-restore-checkpoint.py new file mode 100644 index 0000000000..5e42f4d9b6 --- /dev/null +++ b/tests/gem5/checkpoint-tests/mips-hello-restore-checkpoint.py @@ -0,0 +1,72 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +tests/gem5/checkpoint-tests/mips-hello-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of "mips-hello" binary simulation. +This configuration serves as a test of restoring a checkpoint with MIPS ISA. +""" + +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + + +requires(isa_required=ISA.MIPS) + +cache_hierarchy = NoCache() + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor( + cpu_type=CPUTypes.TIMING, isa=ISA.MIPS, num_cores=2 +) +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload( + obtain_resource("mips-hello"), + checkpoint=CheckpointResource(local_path="./mips-hello-test-checkpoint"), +) + +sim = Simulator(board=board, full_system=False) +sim.run() +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/mips-hello-save-checkpoint.py b/tests/gem5/checkpoint-tests/mips-hello-save-checkpoint.py new file mode 100644 index 0000000000..271d900304 --- /dev/null +++ b/tests/gem5/checkpoint-tests/mips-hello-save-checkpoint.py @@ -0,0 +1,89 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 test script creates a simple board to run the first +10^6 ticks of "mips-hello" binary simulation and saves a checkpoint. +This configuration serves as a test to ensure that checkpoints work +with MIPS ISA. +""" + +import argparse +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + +parser = argparse.ArgumentParser() + +parser.add_argument( + "--checkpoint-path", + type=str, + required=False, + default="mips-hello-test-checkpoint/", + help="The directory to store the checkpoint.", +) + +args = parser.parse_args() + +# This check ensures that the gem5 binary is compiled to the MIPS ISA. +# If not, an exception is thrown. +requires(isa_required=ISA.MIPS) + +cache_hierarchy = NoCache() + +memory = SingleChannelDDR3_1600(size="32MB") + +processor = SimpleProcessor( + cpu_type=CPUTypes.TIMING, isa=ISA.MIPS, num_cores=2 +) + +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) + + +board.set_se_binary_workload(obtain_resource("mips-hello")) + +sim = Simulator(board=board, full_system=False) +max_ticks = 10**6 +sim.run(max_ticks=max_ticks) +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) +print("Taking checkpoint at", args.checkpoint_path) +sim.save_checkpoint(args.checkpoint_path) +print("Done taking checkpoint") diff --git a/tests/gem5/checkpoint-tests/power-hello-restore-checkpoint.py b/tests/gem5/checkpoint-tests/power-hello-restore-checkpoint.py new file mode 100644 index 0000000000..191cd50ec7 --- /dev/null +++ b/tests/gem5/checkpoint-tests/power-hello-restore-checkpoint.py @@ -0,0 +1,72 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +tests/gem5/checkpoint-tests/power-hello-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of "power-hello" binary simulation. +This configuration serves as a test of restoring a checkpoint with POWER ISA. +""" + +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + + +requires(isa_required=ISA.POWER) + +cache_hierarchy = NoCache() + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor( + cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2 +) +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload( + obtain_resource("power-hello"), + checkpoint=obtain_resource("power-hello-test-checkpoint"), +) + +sim = Simulator(board=board, full_system=False) +sim.run() +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/power-hello-save-checkpoint.py b/tests/gem5/checkpoint-tests/power-hello-save-checkpoint.py new file mode 100644 index 0000000000..1dcd421830 --- /dev/null +++ b/tests/gem5/checkpoint-tests/power-hello-save-checkpoint.py @@ -0,0 +1,83 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 test script creates a simple board to run the first +10^6 ticks of "power-hello" binary simulation and saves a checkpoint. +This configuration serves as a test to ensure that checkpoints work +with POWER ISA. +""" + +import argparse +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + +parser = argparse.ArgumentParser() + +parser.add_argument( + "--checkpoint-path", + type=str, + required=False, + default="power-hello-test-checkpoint/", + help="The directory to store the checkpoint.", +) + +args = parser.parse_args() +requires(isa_required=ISA.POWER) + +cache_hierarchy = NoCache() + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor( + cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2 +) + +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload(obtain_resource("power-hello")) + +sim = Simulator(board=board, full_system=False) +max_ticks = 10**6 +sim.run(max_ticks=max_ticks) +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) +print("Taking checkpoint at", args.checkpoint_path) +sim.save_checkpoint(args.checkpoint_path) +print("Done taking checkpoint") diff --git a/tests/gem5/checkpoint-tests/sparc-hello-restore-checkpoint.py b/tests/gem5/checkpoint-tests/sparc-hello-restore-checkpoint.py new file mode 100644 index 0000000000..f8bc3949a5 --- /dev/null +++ b/tests/gem5/checkpoint-tests/sparc-hello-restore-checkpoint.py @@ -0,0 +1,72 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +tests/gem5/checkpoint-tests/sparc-hello-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of "sparc-hello" binary simulation. +This configuration serves as a test of restoring a checkpoint with SPARC ISA. +""" + +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + + +requires(isa_required=ISA.SPARC) + +cache_hierarchy = NoCache() + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor( + cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2 +) +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload( + obtain_resource("sparc-hello"), + checkpoint=CheckpointResource(local_path="./sparc-hello-test-checkpoint"), +) + +sim = Simulator(board=board, full_system=False) +sim.run() +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/sparc-hello-save-checkpoint.py b/tests/gem5/checkpoint-tests/sparc-hello-save-checkpoint.py new file mode 100644 index 0000000000..9c50b5cff9 --- /dev/null +++ b/tests/gem5/checkpoint-tests/sparc-hello-save-checkpoint.py @@ -0,0 +1,80 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 test script creates a simple board to run the first +10^6 ticks of "sparc-hello" binary simulation and saves a checkpoint. +This configuration serves as a test to ensure that checkpoints work +with SPARC ISA. +""" + +import argparse +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + +parser = argparse.ArgumentParser() + +parser.add_argument( + "--checkpoint-path", + type=str, + required=False, + default="sparc-hello-test-checkpoint/", + help="The directory to store the checkpoint.", +) + +args = parser.parse_args() +requires(isa_required=ISA.SPARC) + +cache_hierarchy = NoCache() + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor( + cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2 +) + +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload(obtain_resource("sparc-hello")) + +sim = Simulator(board=board, full_system=False) +max_ticks = 10**6 +sim.run(max_ticks=max_ticks) +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/test-checkpoints.py b/tests/gem5/checkpoint-tests/test-checkpoints.py new file mode 100644 index 0000000000..2edc5785c1 --- /dev/null +++ b/tests/gem5/checkpoint-tests/test-checkpoints.py @@ -0,0 +1,266 @@ +# Copyright (c) 2021-2023 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This runs simple tests to ensure the examples in `configs/example/gem5_library` +still function. They simply check the simulation completed. +""" +from testlib import * +import re +import os + +if config.bin_path: + resource_path = config.bin_path +else: + resource_path = joinpath(absdirpath(__file__), "..", "resources") + +hello_verifier = verifier.MatchRegex(re.compile(r"Hello world!")) +save_checkpoint_verifier = verifier.MatchRegex( + re.compile(r"Done taking checkpoint") +) + + +gem5_verify_config( + name="test-checkpoint-arm-hello-save-checkpoint", + fixtures=(), + verifiers=(save_checkpoint_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "arm-hello-save-checkpoint.py", + ), + config_args=[ + "--checkpoint-path", + joinpath(resource_path, "arm-hello-test-checkpoint"), + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-arm-hello-restore-checkpoint", + fixtures=(), + verifiers=(hello_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "arm-hello-restore-checkpoint.py", + ), + config_args=[], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-x86-hello-save-checkpoint", + fixtures=(), + verifiers=(save_checkpoint_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "x86-hello-save-checkpoint.py", + ), + config_args=[ + "--checkpoint-path", + joinpath(resource_path, "x86-hello-test-checkpoint"), + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-x86-hello-restore-checkpoint", + fixtures=(), + verifiers=(hello_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "x86-hello-restore-checkpoint.py", + ), + config_args=[], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-x86-fs-save-checkpoint", + fixtures=(), + verifiers=(save_checkpoint_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "x86-fs-save-checkpoint.py", + ), + config_args=[ + "--checkpoint-path", + joinpath(resource_path, "x86-fs-test-checkpoint"), + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-x86-fs-restore-checkpoint", + fixtures=(), + verifiers=(), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "x86-fs-restore-checkpoint.py", + ), + config_args=[], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-power-hello-save-checkpoint", + fixtures=(), + verifiers=(save_checkpoint_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "power-hello-save-checkpoint.py", + ), + config_args=[ + "--checkpoint-path", + joinpath(resource_path, "power-hello-test-checkpoint"), + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +gem5_verify_config( + name="test-checkpoint-power-hello-restore-checkpoint", + fixtures=(), + verifiers=(hello_verifier,), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "checkpoint-tests", + "power-hello-restore-checkpoint.py", + ), + config_args=[], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +# gem5_verify_config( +# name="test-checkpoint-mips-hello-save-checkpoint", +# fixtures=(), +# verifiers=(save_checkpoint_verifier,), +# config=joinpath( +# config.base_dir, +# "tests", +# "gem5", +# "checkpoint-tests", +# "mips-hello-save-checkpoint.py", +# ), +# config_args=[ +# # "--checkpoint-path", +# # joinpath(resource_path, "mips-hello-test-checkpoint"), +# ], +# valid_isas=(constants.all_compiled_tag,), +# valid_hosts=constants.supported_hosts, +# length=constants.quick_tag, +# ) + +# gem5_verify_config( +# name="test-checkpoint-mips-hello-restore-checkpoint", +# fixtures=(), +# verifiers=(hello_verifier,), +# config=joinpath( +# config.base_dir, +# "tests", +# "gem5", +# "checkpoint-tests", +# "mips-hello-restore-checkpoint.py", +# ), +# config_args=[], +# valid_isas=(constants.all_compiled_tag,), +# valid_hosts=constants.supported_hosts, +# length=constants.quick_tag, +# ) + +# gem5_verify_config( +# name="test-checkpoint-sparc-hello-save-checkpoint", +# fixtures=(), +# verifiers=(save_checkpoint_verifier,), +# config=joinpath( +# config.base_dir, +# "tests", +# "gem5", +# "checkpoint-tests", +# "sparc-hello-save-checkpoint.py", +# ), +# config_args=[ +# # "--checkpoint-path", +# # joinpath(resource_path, "sparc-hello-test-checkpoint"), +# ], +# valid_isas=(constants.all_compiled_tag,), +# valid_hosts=constants.supported_hosts, +# length=constants.quick_tag, +# ) + +# gem5_verify_config( +# name="test-checkpoint-sparc-hello-restore-checkpoint", +# fixtures=(), +# verifiers=(hello_verifier,), +# config=joinpath( +# config.base_dir, +# "tests", +# "gem5", +# "checkpoint-tests", +# "sparc-hello-restore-checkpoint.py", +# ), +# config_args=[], +# valid_isas=(constants.all_compiled_tag,), +# valid_hosts=constants.supported_hosts, +# length=constants.quick_tag, +# ) diff --git a/tests/gem5/checkpoint-tests/x86-fs-restore-checkpoint.py b/tests/gem5/checkpoint-tests/x86-fs-restore-checkpoint.py new file mode 100644 index 0000000000..f43b931135 --- /dev/null +++ b/tests/gem5/checkpoint-tests/x86-fs-restore-checkpoint.py @@ -0,0 +1,88 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +tests/gem5/checkpoint-tests/x86-fs-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of full system simulation. +This configuration serves as a test of restoring a checkpoint with X86 ISA in fs mode. +""" + +from gem5.components.boards.x86_board import X86Board +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( + PrivateL1PrivateL2CacheHierarchy, +) +from gem5.components.processors.cpu_types import CPUTypes +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.simulate.simulator import Simulator + +# Run a check to ensure the right version of gem5 is being used. +requires(isa_required=ISA.X86) + +# Setup the cache hierarchy. +# For classic, PrivateL1PrivateL2 and NoCache have been tested. +# For Ruby, MESI_Two_Level and MI_example have been tested. +cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( + l1d_size="32kB", l1i_size="32kB", l2_size="512kB" +) + +# Setup the system memory. +memory = SingleChannelDDR3_1600(size="1GB") + +# Setup a single core Processor. +processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1) + +# Setup the board. +board = X86Board( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) + +# Set the Full System workload. +board.set_kernel_disk_workload( + kernel=obtain_resource("x86-linux-kernel-5.4.49"), + disk_image=obtain_resource("x86-ubuntu-18.04-img"), + checkpoint=obtain_resource("x86-fs-test-checkpoint"), +) + +sim = Simulator(board=board, full_system=True) +print("Beginning simulation!") + +sim.run(max_ticks=10**10) + +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/x86-fs-save-checkpoint.py b/tests/gem5/checkpoint-tests/x86-fs-save-checkpoint.py new file mode 100644 index 0000000000..87741235f0 --- /dev/null +++ b/tests/gem5/checkpoint-tests/x86-fs-save-checkpoint.py @@ -0,0 +1,101 @@ +# Copyright (c) 2021 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 test script creates a simple board to run the first +10^6 ticks of x86 full system kernel disk workload simulation and saves a checkpoint. +This configuration serves as a test to ensure that checkpoints work +with X86 ISA in fs mode. +""" + +import argparse +from gem5.components.boards.x86_board import X86Board +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( + PrivateL1PrivateL2CacheHierarchy, +) +from gem5.components.processors.cpu_types import CPUTypes +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator + +parser = argparse.ArgumentParser() + +parser.add_argument( + "--checkpoint-path", + type=str, + required=False, + default="x86-fs-test-checkpoint/", + help="The directory to store the checkpoint.", +) + +args = parser.parse_args() + +# Run a check to ensure the right version of gem5 is being used. +requires(isa_required=ISA.X86) + +# Setup the cache hierarchy. +# For classic, PrivateL1PrivateL2 and NoCache have been tested. +# For Ruby, MESI_Two_Level and MI_example have been tested. +cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( + l1d_size="32kB", l1i_size="32kB", l2_size="512kB" +) + +# Setup the system memory. +memory = SingleChannelDDR3_1600(size="1GB") + +# Setup a single core Processor. +processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1) + +# Setup the board. +board = X86Board( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) + +# Set the Full System workload. +board.set_kernel_disk_workload( + kernel=obtain_resource("x86-linux-kernel-5.4.49"), + disk_image=obtain_resource("x86-ubuntu-18.04-img"), +) + +sim = Simulator(board=board, full_system=True) +print("Beginning simulation!") + +max_ticks = 10**6 +sim.run(max_ticks=max_ticks) +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) +print("Taking checkpoint at", args.checkpoint_path) +sim.save_checkpoint(args.checkpoint_path) +print("Done taking checkpoint") diff --git a/tests/gem5/checkpoint-tests/x86-hello-restore-checkpoint.py b/tests/gem5/checkpoint-tests/x86-hello-restore-checkpoint.py new file mode 100644 index 0000000000..8562751708 --- /dev/null +++ b/tests/gem5/checkpoint-tests/x86-hello-restore-checkpoint.py @@ -0,0 +1,72 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +tests/gem5/checkpoint-tests/x86-hello-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of "x86-hello64-static" binary simulation. +This configuration serves as a test of restoring a checkpoint with X86 ISA. +""" + +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import ( + PrivateL1CacheHierarchy, +) +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + + +requires(isa_required=ISA.X86) + +cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB") + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4) +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload( + obtain_resource("x86-hello64-static"), + checkpoint=obtain_resource("x86-hello-test-checkpoint"), +) + +sim = Simulator(board=board, full_system=False) +sim.run() +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) diff --git a/tests/gem5/checkpoint-tests/x86-hello-save-checkpoint.py b/tests/gem5/checkpoint-tests/x86-hello-save-checkpoint.py new file mode 100644 index 0000000000..5211230af6 --- /dev/null +++ b/tests/gem5/checkpoint-tests/x86-hello-save-checkpoint.py @@ -0,0 +1,83 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 test script creates a simple board to run the first +10^6 ticks of "x86-hello64-static" binary simulation and saves a checkpoint. +This configuration serves as a test to ensure that checkpoints work +with X86 ISA. +""" + +import argparse +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import obtain_resource +from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import ( + PrivateL1CacheHierarchy, +) +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes + +parser = argparse.ArgumentParser() + +parser.add_argument( + "--checkpoint-path", + type=str, + required=False, + default="x86-hello-test-checkpoint/", + help="The directory to store the checkpoint.", +) + +args = parser.parse_args() +requires(isa_required=ISA.X86) + +cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB") + +memory = SingleChannelDDR3_1600(size="32MB") +processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4) + +board = SimpleBoard( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) +board.set_se_binary_workload(obtain_resource("x86-hello64-static")) + +sim = Simulator(board=board, full_system=False) +max_ticks = 10**6 +sim.run(max_ticks=max_ticks) +print( + "Exiting @ tick {} because {}.".format( + sim.get_current_tick(), sim.get_last_exit_event_cause() + ) +) +print("Taking checkpoint at", args.checkpoint_path) +sim.save_checkpoint(args.checkpoint_path) +print("Done taking checkpoint")