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Make microOp vs microop and macroOp vs macroop capitilization consistent.

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src/arch/x86/isa/macroop.isa:
    Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
    Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.

--HG--
extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
This commit is contained in:
Gabe Black
2007-06-12 16:21:47 +00:00
parent 1493ceda8f
commit a7f3bbcfab
12 changed files with 126 additions and 100 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/cpu/exetrace.cc
View File

@@ -162,7 +162,7 @@ Trace::InstRecord::dump()
static int fd = 0;
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
if(!staticInst->isMicroop() || staticInst->isLastMicroop())
{
if(!cosim_listener)
{
@@ -245,7 +245,7 @@ Trace::InstRecord::dump()
#if 0 //THE_ISA == SPARC_ISA
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
if(!staticInst->isMicroop() || staticInst->isLastMicroop())
{
static uint64_t regs[32] = {
0, 0, 0, 0, 0, 0, 0, 0,
@@ -432,7 +432,7 @@ Trace::InstRecord::dump()
setupSharedData();
// We took a trap on a micro-op...
if (wasMicro && !staticInst->isMicroOp())
if (wasMicro && !staticInst->isMicroop())
{
// let's skip comparing this tick
while (!compared)
@@ -444,13 +444,13 @@ Trace::InstRecord::dump()
wasMicro = false;
}
if (staticInst->isLastMicroOp())
if (staticInst->isLastMicroop())
wasMicro = false;
else if (staticInst->isMicroOp())
else if (staticInst->isMicroop())
wasMicro = true;
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
while (!compared) {
if (shared_data->flags == OWN_M5) {
m5Pc = PC & TheISA::PAddrImplMask;

4
src/cpu/simple/atomic.cc
View File

@@ -540,8 +540,8 @@ AtomicSimpleCPU::tick()
}
// @todo remove me after debugging with legion done
if (curStaticInst && (!curStaticInst->isMicroOp() ||
curStaticInst->isFirstMicroOp()))
if (curStaticInst && (!curStaticInst->isMicroop() ||
curStaticInst->isFirstMicroop()))
instCnt++;
if (simulate_stalls) {

8
src/cpu/simple/base.cc
View File

@@ -400,17 +400,17 @@ BaseSimpleCPU::preExecute()
//If we decoded an instruction and it's microcoded, start pulling
//out micro ops
if (instPtr && instPtr->isMacroOp()) {
if (instPtr && instPtr->isMacroop()) {
curMacroStaticInst = instPtr;
curStaticInst = curMacroStaticInst->
fetchMicroOp(thread->readMicroPC());
fetchMicroop(thread->readMicroPC());
} else {
curStaticInst = instPtr;
}
} else {
//Read the next micro op from the macro op
curStaticInst = curMacroStaticInst->
fetchMicroOp(thread->readMicroPC());
fetchMicroop(thread->readMicroPC());
}
//If we decoded an instruction this "tick", record information about it.
@@ -475,7 +475,7 @@ BaseSimpleCPU::advancePC(Fault fault)
thread->setNextMicroPC(1);
} else {
//If we're at the last micro op for this instruction
if (curStaticInst && curStaticInst->isLastMicroOp()) {
if (curStaticInst && curStaticInst->isLastMicroop()) {
//We should be working with a macro op
assert(curMacroStaticInst);
//Close out this macro op, and clean up the

4
src/cpu/static_inst.cc
View File

@@ -76,9 +76,9 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
}
StaticInstPtr
StaticInst::fetchMicroOp(MicroPC micropc)
StaticInst::fetchMicroop(MicroPC micropc)
{
panic("StaticInst::fetchMicroOp() called on instruction "
panic("StaticInst::fetchMicroop() called on instruction "
"that is not microcoded.");
}

18
src/cpu/static_inst.hh
View File

@@ -143,11 +143,11 @@ class StaticInstBase : public RefCounted
IsUnverifiable, ///< Can't be verified by a checker
//Flags for microcode
IsMacroOp, ///< Is a macroop containing microops
IsMicroOp, ///< Is a microop
IsMacroop, ///< Is a macroop containing microops
IsMicroop, ///< Is a microop
IsDelayedCommit, ///< This microop doesn't commit right away
IsLastMicroOp, ///< This microop ends a microop sequence
IsFirstMicroOp, ///< This microop begins a microop sequence
IsLastMicroop, ///< This microop ends a microop sequence
IsFirstMicroop, ///< This microop begins a microop sequence
//This flag doesn't do anything yet
IsMicroBranch, ///< This microop branches within the microcode for a macroop
@@ -242,11 +242,11 @@ class StaticInstBase : public RefCounted
bool isQuiesce() const { return flags[IsQuiesce]; }
bool isIprAccess() const { return flags[IsIprAccess]; }
bool isUnverifiable() const { return flags[IsUnverifiable]; }
bool isMacroOp() const { return flags[IsMacroOp]; }
bool isMicroOp() const { return flags[IsMicroOp]; }
bool isMacroop() const { return flags[IsMacroop]; }
bool isMicroop() const { return flags[IsMicroop]; }
bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
bool isLastMicroop() const { return flags[IsLastMicroop]; }
bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
//This flag doesn't do anything yet
bool isMicroBranch() const { return flags[IsMicroBranch]; }
//@}
@@ -369,7 +369,7 @@ class StaticInst : public StaticInstBase
* Return the microop that goes with a particular micropc. This should
* only be defined/used in macroops which will contain microops
*/
virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
virtual StaticInstPtr fetchMicroop(MicroPC micropc);
/**
* Return the target address for a PC-relative branch.