From a764b9be1c0c4b701c8ebb8812e0eaf7a2eecec9 Mon Sep 17 00:00:00 2001
From: Ivana Mitrovic <imitrovic@ucdavis.edu>
Date: Tue, 4 Jun 2024 10:26:53 -0700
Subject: [PATCH] Revert "arch-x86: Fix TLB Assertion Error on CFLUSH" (#1196)

Reverts gem5/gem5#1080 as it is not a good fix.
---
 src/cpu/translation.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 52ef134091..2156a50e8f 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -254,7 +254,7 @@ class DataTranslation : public BaseMMU::Translation
            BaseMMU::Mode mode)
     {
         assert(state);
-        assert(mode == state->mode || req->isCacheClean());
+        assert(mode == state->mode);
         if (state->finish(fault, index)) {
             if (state->getFault() == NoFault) {
                 // Don't access the request if faulted (due to squash)