From a6fc2797e8ac2af5f13cc8c2881671a4f0191d3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eduardo=20Jos=C3=A9=20G=C3=B3mez=20Hern=C3=A1ndez?= Date: Tue, 6 Apr 2021 16:38:52 +0200 Subject: [PATCH] arch-x86: Fixed locked cmpxchg8b allows reordering Locked versions of cmpxcgh8b (and cmpxcgh16b) should be guarded by mfences to prevent reordering from surrounding memory instructions. Change-Id: I4a04bb871b4f9a38efd78df194b43f785d5d2236 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44166 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/x86/isa/insts/general_purpose/semaphores.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py index de7c6ef631..aae67fac70 100644 --- a/src/arch/x86/isa/insts/general_purpose/semaphores.py +++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py @@ -132,6 +132,7 @@ cmpxchg8bCode = ''' def macroop CMPXCHG8B_%(suffix)s { .adjust_env clampOsz %(rdip)s + %(mfence)s lea t1, seg, %(sib)s, disp, dataSize=asz ldsplit%(l)s (t2, t3), seg, [1, t0, t1], disp=0 @@ -150,20 +151,25 @@ doneComparing: # Write to memory stsplit%(ul)s (t2, t3), seg, [1, t0, t1], disp=0 + %(mfence)s }; ''' microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib", "l": "", "ul": "", + "mfence": "", "suffix": "M"} microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel", "l": "", "ul": "", + "mfence": "", "suffix": "P"} microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib", "l": "l", "ul": "ul", + "mfence": "mfence", "suffix": "LOCKED_M"} microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel", "l": "l", "ul": "ul", + "mfence": "mfence", "suffix": "LOCKED_P"} #let {{