diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 1a5d0e5b12..2b5935dee5 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -849,8 +849,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
   {
     assert(is_valid(cache_entry));
     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    L1Icache.setMRU(address);
-    L1Dcache.setMRU(address);
+    // Request misses and new replacement policy info is set for new entry.
+    // No need to setMRU on external hit.
     sequencer.readCallback(address, cache_entry.DataBlk, true);
   }
 
@@ -867,8 +867,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
   {
     assert(is_valid(cache_entry));
     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    L1Icache.setMRU(address);
-    L1Dcache.setMRU(address);
+    // Request misses and new replacement policy info is set for new entry.
+    // No need to setMRU on external hit.
     sequencer.writeCallback(address, cache_entry.DataBlk, true);
     cache_entry.Dirty := true;
   }