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isa,cpu: Add support for FS SMT Interrupts

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Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
This commit is contained in:
Mitch Hayenga
2015-09-30 11:14:19 -05:00
parent e255fa053f
commit a5c4eb3de9
23 changed files with 129 additions and 102 deletions
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6
configs/example/se.py
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@@ -265,9 +265,9 @@ if options.ruby:
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts.pio = ruby_port.master
system.cpu[i].interrupts.int_master = ruby_port.slave
system.cpu[i].interrupts.int_slave = ruby_port.master
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else: