arch-x86: Add instructions from SSE4.1 set.

The following instructions were implemented: PHMINPOSUW, ROUNDSS, ROUNDSD, EXTRACTPS, INSERTPS, PMULLD, PMULDQ,
PCMPGTQ, PMINUW, PMINUD, PMINSB, MINSD, PMAXUW, PMAXUD, PMAXSB, PMAXSD, PEXTRB, PEXTRW for memory, PEXTRD, PEXTRQ,
PINSRB, PINSRD, PINSRQ, PACKUSDW, PBLENDW, BLENDPS, BLENDPD, BLENDVPD, BLENDVPS, PBLENDVB, PMOVSXDQ, PMOVSXWQ,
PMOVSXWD, PMOVSXBQ, PMOVSXBD, PMOVSXBW, PMOVZXDQ, PMOVZXWQ, PMOVZXWD, PMOVZXWD, PMOVZXBQ, PMOVZXBD, PMOVZXBW.

Also fix bug in PACKUSWB_XMM_M, it was marked as sign operation, though it is unsigned.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1308

Change-Id: I1a8d26c0426690841dcc80a6fa5dcffb8cbc5d9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67737
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

src/base/bitfield.hh

@@ -131,6 +131,22 @@ sext(uint64_t val)
     return val;
 }
 
+/**
+ * Sign-extend an N-bit value to 64 bits. Assumes all bits past the sign are
+ * currently zero. For true sign extension regardless of the value of the sign
+ * bit, see szext.
+ *
+ * @ingroup api_bitfield
+ */
+constexpr uint64_t
+sext(uint64_t val, int N)
+{
+    bool sign_bit = bits(val, N - 1);
+    if (sign_bit)
+        val |= ~mask(N);
+    return val;
+}
+
 /**
  * Sign-extend an N-bit value to 64 bits. Zero any bits past the sign if
  * necessary.