From a4c96002007eebd99a72e1afa6fdf621bd4bbf98 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Wed, 27 Sep 2023 18:58:06 +0100
Subject: [PATCH] arch-arm: Move generateTrap from MiscRegOp to ArmStaticInst

System(Misc) register accesses are not the only trappable instructions.
We move the exception generation logic (generateTrap) from the
MiscRegOp64 to the base ArmStaticInst

Change-Id: Ie2ba0c39790f50e3e8d504d153025d402283ec95
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
---
 src/arch/arm/insts/misc64.cc      | 16 ----------------
 src/arch/arm/insts/misc64.hh      |  3 +--
 src/arch/arm/insts/static_inst.cc | 15 +++++++++++++++
 src/arch/arm/insts/static_inst.hh |  4 ++++
 4 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 4ad44bfc63..bb1de2cc94 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -128,22 +128,6 @@ MiscRegOp64::generateTrap(ExceptionLevel el) const
     return generateTrap(el, ExceptionClass::TRAPPED_MSR_MRS_64, iss());
 }
 
-Fault
-MiscRegOp64::generateTrap(ExceptionLevel el, ExceptionClass ec,
-        uint32_t iss) const
-{
-    switch (el) {
-      case EL1:
-        return std::make_shared<SupervisorTrap>(getEMI(), iss, ec);
-      case EL2:
-        return std::make_shared<HypervisorTrap>(getEMI(), iss, ec);
-      case EL3:
-        return std::make_shared<SecureMonitorTrap>(getEMI(), iss, ec);
-      default:
-        panic("Invalid EL: %d\n", el);
-    }
-}
-
 RegVal
 MiscRegImmOp64::miscRegImm() const
 {
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 78c29e585e..6b94099262 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -174,9 +174,8 @@ class MiscRegOp64 : public ArmISA::ArmStaticInst
 
     bool miscRead() const { return _miscRead; }
 
+    using ArmISA::ArmStaticInst::generateTrap;
     Fault generateTrap(ArmISA::ExceptionLevel el) const;
-    Fault generateTrap(ArmISA::ExceptionLevel el,
-            ArmISA::ExceptionClass ec, uint32_t iss) const;
 };
 
 class MiscRegImmOp64 : public MiscRegOp64
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index a645b39270..86e8cdfa5c 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1367,6 +1367,21 @@ ArmStaticInst::getCurSmeVecLenInBits(ThreadContext *tc)
     return isa->getCurSmeVecLenInBits();
 }
 
+Fault
+ArmStaticInst::generateTrap(ExceptionLevel el, ExceptionClass ec,
+        uint32_t iss) const
+{
+    switch (el) {
+      case EL1:
+        return std::make_shared<SupervisorTrap>(getEMI(), iss, ec);
+      case EL2:
+        return std::make_shared<HypervisorTrap>(getEMI(), iss, ec);
+      case EL3:
+        return std::make_shared<SecureMonitorTrap>(getEMI(), iss, ec);
+      default:
+        panic("Invalid EL: %d\n", el);
+    }
+}
 
 } // namespace ArmISA
 } // namespace gem5
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index cc96dd9269..484017fe88 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -633,6 +633,10 @@ class ArmStaticInst : public StaticInst
         return std::make_shared<UndefinedInstruction>(
             machInst, false, mnemonic, disabled);
     }
+
+    Fault
+    generateTrap(ArmISA::ExceptionLevel el,
+                 ArmISA::ExceptionClass ec, uint32_t iss) const;
 };
 
 } // namespace ArmISA