diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 12ab132072..b612516fcc 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1225,6 +1225,17 @@ AbortFault<T>::isMMUFault() const
          (source <  ArmFault::PermissionLL + 4));
 }
 
+template<class T>
+bool
+AbortFault<T>::isExternalAbort() const
+{
+    return
+        (source == ArmFault::SynchronousExternalAbort)  ||
+        (source == ArmFault::AsynchronousExternalAbort) ||
+        ((source >= ArmFault::SynchExtAbtOnTranslTableWalkLL) &&
+         (source < ArmFault::SynchExtAbtOnTranslTableWalkLL + 4));
+}
+
 template<class T>
 bool
 AbortFault<T>::getFaultVAddr(Addr &va) const
@@ -1368,6 +1379,7 @@ DataAbort::iss() const
     iss.wnr = write;
     iss.s1ptw = s1ptw;
     iss.cm = cm;
+    iss.ea = isExternalAbort();
 
     // ISS is valid if not caused by a stage 1 page table walk, and when taken
     // to AArch64 only when directed to EL2
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index ac100208a3..a76439574a 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -254,6 +254,7 @@ class ArmFault : public FaultBase
     virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
     virtual bool getFaultVAddr(Addr &va) const { return false; }
     OperatingMode getToMode() const { return toMode; }
+    virtual bool isExternalAbort() const { return false; }
 };
 
 template<typename T>
@@ -511,6 +512,7 @@ class AbortFault : public ArmFaultVals<T>
     void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
     void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
     bool isMMUFault() const;
+    bool isExternalAbort() const override;
 };
 
 class PrefetchAbort : public AbortFault<PrefetchAbort>