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arch,cpu: Remove the idea of a zero register.

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This is now handled by using the InvalidRegClass.

Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49746
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-22 06:04:31 -07:00
parent caffb4e1ff
commit a40950a5c9
30 changed files with 42 additions and 131 deletions
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6
src/cpu/simple_thread.hh
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@@ -408,9 +408,6 @@ class SimpleThread : public ThreadState, public ThreadContext
auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
if (reg.index() == reg_class.zeroReg())
return;
DPRINTFV(reg_class.debug(), "Setting %s register %s (%d) to %#x.\n",
reg.className(), reg_class.regName(arch_reg), idx, val);
reg_file.reg(idx) = val;
@@ -427,9 +424,6 @@ class SimpleThread : public ThreadState, public ThreadContext
auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
if (reg.index() == reg_class.zeroReg())
return;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
reg.className(), idx, val);
reg_file.reg(idx) = val;