diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b5f3d078bf..a151334c49 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -131,6 +131,13 @@ void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         tc->clearArchRegs();
     }
 
+    tc->setMiscReg(MISCREG_PRV, PRV_M);
+    STATUS status = tc->readMiscReg(MISCREG_STATUS);
+    status.mie = 0;
+    status.mprv = 0;
+    tc->setMiscReg(MISCREG_STATUS, status);
+    tc->setMiscReg(MISCREG_MCAUSE, 0);
+
     // Advance the PC to the implementation-defined reset vector
     PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
     tc->pcState(pc);
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d9cb44c3d6..2176f889bd 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -95,24 +95,15 @@ class RiscvFault : public FaultBase
 
 class Reset : public FaultBase
 {
+  private:
+    const FaultName _name;
 
-    public:
-        Reset()
-            : _name("reset")
-        {}
+  public:
+    Reset() : _name("reset") {}
+    FaultName name() const override { return _name; }
 
-        FaultName
-        name() const override
-        {
-            return _name;
-        }
-
-        void
-        invoke(ThreadContext *tc, const StaticInstPtr &inst =
-            StaticInst::nullStaticInstPtr) override;
-
-    private:
-        const FaultName _name;
+    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+        StaticInst::nullStaticInstPtr) override;
 };
 
 class InstFault : public RiscvFault