diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py index bce7f2497f..5d53c882aa 100644 --- a/src/arch/riscv/RiscvISA.py +++ b/src/arch/riscv/RiscvISA.py @@ -74,6 +74,16 @@ class RiscvType(Enum): vals = ["RV32", "RV64"] +class PrivilegeModeSet(Enum): + vals = [ + "M", # Machine privilege mode only + "MU", # Machine and user privlege modes implemented + "MNU", # MU privilege modes with user-mode trap + "MSU", # Machine, supervisor and user modes implemented + "MNSU", # MSU privilege modes with user-mode trap + ] + + class RiscvISA(BaseISA): type = "RiscvISA" cxx_class = "gem5::RiscvISA::ISA" @@ -95,6 +105,11 @@ class RiscvISA(BaseISA): "Length of each vector element in bits. \ ELEN in Ch. 2 of RISC-V vector spec", ) + privilege_mode_set = Param.PrivilegeModeSet( + "MSU", + "The combination of privilege modes \ + in Privilege Levels section of RISC-V privileged spec", + ) enable_Zicbom_fs = Param.Bool(True, "Enable Zicbom extension in FS mode") enable_Zicboz_fs = Param.Bool(True, "Enable Zicboz extension in FS mode") diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript index d3dd1d5970..41da97bcc1 100644 --- a/src/arch/riscv/SConscript +++ b/src/arch/riscv/SConscript @@ -73,7 +73,7 @@ SimObject('RiscvFsWorkload.py', SimObject('RiscvInterrupts.py', sim_objects=['RiscvInterrupts'], tags='riscv isa') SimObject('RiscvISA.py', sim_objects=['RiscvISA'], - enums=['RiscvType'], tags='riscv isa') + enums=['RiscvType', 'PrivilegeModeSet'], tags='riscv isa') SimObject('RiscvMMU.py', sim_objects=['RiscvMMU'], tags='riscv isa') SimObject('RiscvSeWorkload.py', sim_objects=[ 'RiscvSEWorkload', 'RiscvEmuLinux'], tags='riscv isa') diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index 7d4e9f90b6..2e583e3680 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -67,6 +67,7 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) if (FullSystem) { PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV); PrivilegeMode prv = PRV_M; + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); STATUS status = tc->readMiscReg(MISCREG_STATUS); // According to riscv-privileged-v1.11, if a NMI occurs at the middle @@ -82,18 +83,18 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) } else if (isInterrupt()) { if (pp != PRV_M && bits(tc->readMiscReg(MISCREG_MIDELEG), _code) != 0) { - prv = PRV_S; + prv = (misa.rvs) ? PRV_S : ((misa.rvn) ? PRV_U : PRV_M); } - if (pp == PRV_U && + if (pp == PRV_U && misa.rvs && misa.rvn && bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) { prv = PRV_U; } } else { if (pp != PRV_M && bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) { - prv = PRV_S; + prv = (misa.rvs) ? PRV_S : ((misa.rvn) ? PRV_U : PRV_M); } - if (pp == PRV_U && + if (pp == PRV_U && misa.rvs && misa.rvn && bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) { prv = PRV_U; } diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh index d6fa374a14..b003b59426 100644 --- a/src/arch/riscv/interrupts.hh +++ b/src/arch/riscv/interrupts.hh @@ -69,21 +69,41 @@ class Interrupts : public BaseInterrupts { INTERRUPT mask = 0; STATUS status = tc->readMiscReg(MISCREG_STATUS); - INTERRUPT mideleg = tc->readMiscReg(MISCREG_MIDELEG); - INTERRUPT sideleg = tc->readMiscReg(MISCREG_SIDELEG); + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); + INTERRUPT mideleg = 0; + if (misa.rvs || misa.rvn) { + mideleg = tc->readMiscReg(MISCREG_MIDELEG); + } + INTERRUPT sideleg = 0; + if (misa.rvs && misa.rvn) { + sideleg = tc->readMiscReg(MISCREG_SIDELEG); + } PrivilegeMode prv = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV); switch (prv) { case PRV_U: - mask.mei = (!sideleg.mei) | (sideleg.mei & status.uie); - mask.mti = (!sideleg.mti) | (sideleg.mti & status.uie); - mask.msi = (!sideleg.msi) | (sideleg.msi & status.uie); - mask.sei = (!sideleg.sei) | (sideleg.sei & status.uie); - mask.sti = (!sideleg.sti) | (sideleg.sti & status.uie); - mask.ssi = (!sideleg.ssi) | (sideleg.ssi & status.uie); + // status.uie is always 0 if misa.rvn is disabled + if (misa.rvs) { + mask.mei = (!sideleg.mei) | (sideleg.mei & status.uie); + mask.mti = (!sideleg.mti) | (sideleg.mti & status.uie); + mask.msi = (!sideleg.msi) | (sideleg.msi & status.uie); + mask.sei = (!sideleg.sei) | (sideleg.sei & status.uie); + mask.sti = (!sideleg.sti) | (sideleg.sti & status.uie); + mask.ssi = (!sideleg.ssi) | (sideleg.ssi & status.uie); + } else { + // According to the RISC-V privilege spec v1.10, if the + // S privilege mode is not implemented and user-trap + // support, setting mideleg/medeleg bits will delegate the + // trap to U-mode trap handler + mask.mei = (!mideleg.mei) | (mideleg.mei & status.uie); + mask.mti = (!mideleg.mti) | (mideleg.mti & status.uie); + mask.msi = (!mideleg.msi) | (mideleg.msi & status.uie); + mask.sei = mask.sti = mask.ssi = 0; + } if (status.uie) mask.uei = mask.uti = mask.usi = 1; break; case PRV_S: + // status.sie is always 0 if misa.rvn is disabled mask.mei = (!mideleg.mei) | (mideleg.mei & status.sie); mask.mti = (!mideleg.mti) | (mideleg.mti & status.sie); mask.msi = (!mideleg.msi) | (mideleg.msi & status.sie); diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index 0ba6d15b6c..18e9b5fce2 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -254,9 +254,10 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace -ISA::ISA(const Params &p) :BaseISA(p), +ISA::ISA(const Params &p) : BaseISA(p), _rvType(p.riscv_type), checkAlignment(p.check_alignment), - enableRvv(p.enable_rvv),vlen(p.vlen),elen(p.elen) + enableRvv(p.enable_rvv), vlen(p.vlen), elen(p.elen), + _privilegeModeSet(p.privilege_mode_set) { _regClasses.push_back(&intRegClass); _regClasses.push_back(&floatRegClass); @@ -324,8 +325,25 @@ void ISA::clear() // default config arch isa string is rv64(32)imafdc misa.rvi = misa.rvm = misa.rva = misa.rvf = misa.rvd = misa.rvc = 1; - // default privlege modes if MSU - misa.rvs = misa.rvu = 1; + + switch (getPrivilegeModeSet()) { + case enums::M: + break; + case enums::MU: + misa.rvu = 1; + break; + case enums::MNU: + misa.rvu = misa.rvn = 1; + break; + case enums::MSU: + misa.rvs = misa.rvu = 1; + break; + case enums::MNSU: + misa.rvs = misa.rvu = misa.rvn = 1; + break; + default: + panic("Privilege mode set config should not reach here"); + } // mark FS is initial status.fs = INITIAL; @@ -510,6 +528,24 @@ ISA::readMiscReg(RegIndex idx) default: panic("%s: Unknown _rvType: %d", name(), (int)_rvType); } + // Check status.mpp + MISA misa = readMiscRegNoEffect(MISCREG_ISA); + switch(status.mpp) { + case PRV_U: + status.mpp = (misa.rvu) ? PRV_U : PRV_M; + break; + case PRV_S: + if (misa.rvs) + status.mpp = PRV_S; + else + status.mpp = (misa.rvu) ? PRV_U : PRV_M; + break; + case PRV_M: + break; + default: + status.mpp = (misa.rvu) ? PRV_U : PRV_M; + } + setMiscRegNoEffect(idx, status); return readMiscRegNoEffect(idx); @@ -697,6 +733,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val) if (!getEnableRvv()) { new_misa.rvv = 0; } + new_misa.rvn = cur_misa.rvn; + new_misa.rvs = cur_misa.rvs; + new_misa.rvu = cur_misa.rvu; setMiscRegNoEffect(idx, new_misa); } break; diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 66cba0f7fa..9a24a76745 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -94,6 +94,11 @@ class ISA : public BaseISA */ unsigned elen; + /** The combination of privilege modes + * in Privilege Levels section of RISC-V privileged spec + */ + PrivilegeModeSet _privilegeModeSet; + public: using Params = RiscvISAParams; @@ -124,7 +129,7 @@ class ISA : public BaseISA virtual const std::unordered_map& getCSRMaskMap() const { - return CSRMasks[_rvType]; + return CSRMasks[_rvType][_privilegeModeSet]; } bool alignmentCheckEnabled() const { return checkAlignment; } @@ -164,6 +169,8 @@ class ISA : public BaseISA unsigned getVecLenInBytes() { return vlen >> 3; } unsigned getVecElemLenInBits() { return elen; } + PrivilegeModeSet getPrivilegeModeSet() { return _privilegeModeSet; } + virtual Addr getFaultHandlerAddr( RegIndex idx, uint64_t cause, bool intr) const; }; diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 340e5b5d68..4a6eed2e89 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -4595,6 +4595,12 @@ decode QUADRANT default Unknown::unknown() { xc->pcState()); }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 0x2: uret({{ + MISA misa = xc->readMiscReg(MISCREG_ISA); + if (!misa.rvn) { + return std::make_shared( + "sret can't execute without N systems", + machInst); + } STATUS status = xc->readMiscReg(MISCREG_STATUS); status.uie = status.upie; status.upie = 1; @@ -4604,6 +4610,12 @@ decode QUADRANT default Unknown::unknown() { } 0x8: decode RS2 { 0x2: sret({{ + MISA misa = xc->readMiscReg(MISCREG_ISA); + if (!misa.rvs) { + return std::make_shared( + "sret can't execute without RVS", + machInst); + } STATUS status = xc->readMiscReg(MISCREG_STATUS); auto pm = (PrivilegeMode)xc->readMiscReg( MISCREG_PRV); @@ -4623,11 +4635,12 @@ decode QUADRANT default Unknown::unknown() { } }}, IsSerializeAfter, IsNonSpeculative, IsReturn); 0x5: wfi({{ + MISA misa = xc->readMiscReg(MISCREG_ISA); STATUS status = xc->readMiscReg(MISCREG_STATUS); auto pm = (PrivilegeMode)xc->readMiscReg( MISCREG_PRV); - if (pm == PRV_U || - (pm == PRV_S && status.tw == 1)) { + if (misa.rvs && (pm == PRV_U || + (pm == PRV_S && status.tw == 1))) { return std::make_shared( "wfi in user mode or TW enabled", machInst); @@ -4647,6 +4660,12 @@ decode QUADRANT default Unknown::unknown() { IsSerializeAfter, No_OpClass); } 0x9: sfence_vma({{ + MISA misa = xc->readMiscReg(MISCREG_ISA); + if (!misa.rvs) { + return std::make_shared( + "sfence_vma can't execute without RVS", + machInst); + } STATUS status = xc->readMiscReg(MISCREG_STATUS); auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) { diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 98b0af1e2d..051c526377 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -334,6 +334,7 @@ def template CSRExecute {{ auto isa = static_cast(xc->tcBase()->getIsaPtr()); auto& csr_data = isa->getCSRDataMap(); auto& csr_masks = isa->getCSRMaskMap(); + MISA misa = isa->readMiscRegNoEffect(MISCREG_ISA); auto csr_data_it = csr_data.find(csr); if (csr_data_it == csr_data.end()) { @@ -351,6 +352,14 @@ def template CSRExecute {{ machInst); } + MISA csr_exts = csr_data_it->second.isaExts; + if ((csr_exts & misa) != csr_exts) { + return std::make_shared( + csprintf("%s is not support in the isa spec %d\n", + csrName), + machInst); + } + auto mask_it = csr_masks.find(csr); RegVal maskVal = (mask_it == csr_masks.end()) ? mask(64) : mask_it->second; diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh index 91fb507034..62ecd9f960 100644 --- a/src/arch/riscv/pcstate.hh +++ b/src/arch/riscv/pcstate.hh @@ -44,6 +44,7 @@ #include "arch/generic/pcstate.hh" #include "arch/riscv/regs/vector.hh" +#include "enums/PrivilegeModeSet.hh" #include "enums/RiscvType.hh" namespace gem5 @@ -55,6 +56,8 @@ using RiscvType = enums::RiscvType; constexpr enums::RiscvType RV32 = enums::RV32; constexpr enums::RiscvType RV64 = enums::RV64; +using PrivilegeModeSet = enums::PrivilegeModeSet; + class PCState : public GenericISA::UPCState<4> { protected: diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index cd00f5d63a..a9ad7b1d32 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -106,6 +106,10 @@ RiscvProcess64::initState() tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U); auto *isa = dynamic_cast(tc->getIsaPtr()); fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits mode"); + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); + fatal_if(!(misa.rvu && misa.rvs), + "RISC V SE mode can't run without supervisor and user " + "privilege modes."); } } @@ -120,6 +124,10 @@ RiscvProcess32::initState() tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U); auto *isa = dynamic_cast(tc->getIsaPtr()); fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits mode"); + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); + fatal_if(!(misa.rvu && misa.rvs), + "RISC V SE mode can't run without supervisor and user " + "privilege modes."); } } diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh index d36776d7ef..96e88c7438 100644 --- a/src/arch/riscv/regs/misc.hh +++ b/src/arch/riscv/regs/misc.hh @@ -500,6 +500,7 @@ struct CSRMetadata const std::string name; const int physIndex; const uint64_t rvTypes; + const uint64_t isaExts; }; template @@ -507,474 +508,660 @@ constexpr uint64_t rvTypeFlags(T... args) { return ((1 << args) | ...); } +template +constexpr uint64_t isaExtsFlags(T... isa_exts) { + return ((1ULL << (isa_exts - 'a')) | ...); +} + +constexpr uint64_t isaExtsFlags() { + return 0ULL; +} + const std::unordered_map CSRData = { {CSR_USTATUS, - {"ustatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32)}}, + {"ustatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32), + isaExtsFlags('n')}}, {CSR_UIE, - {"uie", MISCREG_IE, rvTypeFlags(RV64, RV32)}}, + {"uie", MISCREG_IE, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}}, {CSR_UTVEC, - {"utvec", MISCREG_UTVEC, rvTypeFlags(RV64, RV32)}}, + {"utvec", MISCREG_UTVEC, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}}, {CSR_USCRATCH, - {"uscratch", MISCREG_USCRATCH, rvTypeFlags(RV64, RV32)}}, + {"uscratch", MISCREG_USCRATCH, rvTypeFlags(RV64, RV32), + isaExtsFlags('n')}}, {CSR_UEPC, - {"uepc", MISCREG_UEPC, rvTypeFlags(RV64, RV32)}}, + {"uepc", MISCREG_UEPC, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}}, {CSR_UCAUSE, - {"ucause", MISCREG_UCAUSE, rvTypeFlags(RV64, RV32)}}, + {"ucause", MISCREG_UCAUSE, rvTypeFlags(RV64, RV32), + isaExtsFlags('n')}}, {CSR_UTVAL, - {"utval", MISCREG_UTVAL, rvTypeFlags(RV64, RV32)}}, + {"utval", MISCREG_UTVAL, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}}, {CSR_UIP, - {"uip", MISCREG_IP, rvTypeFlags(RV64, RV32)}}, + {"uip", MISCREG_IP, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}}, {CSR_FFLAGS, - {"fflags", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32)}}, + {"fflags", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32), + isaExtsFlags('f')}}, {CSR_FRM, - {"frm", MISCREG_FRM, rvTypeFlags(RV64, RV32)}}, + {"frm", MISCREG_FRM, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}}, // Actually FRM << 5 | FFLAGS {CSR_FCSR, - {"fcsr", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32)}}, + {"fcsr", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}}, {CSR_CYCLE, - {"cycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32)}}, + {"cycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_TIME, - {"time", MISCREG_TIME, rvTypeFlags(RV64, RV32)}}, + {"time", MISCREG_TIME, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_INSTRET, - {"instret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32)}}, + {"instret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_HPMCOUNTER03, - {"hpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER04, - {"hpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER05, - {"hpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER06, - {"hpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER07, - {"hpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER08, - {"hpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER09, - {"hpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER10, - {"hpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER11, - {"hpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER12, - {"hpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER13, - {"hpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER14, - {"hpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER15, - {"hpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER16, - {"hpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER17, - {"hpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER18, - {"hpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER19, - {"hpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER20, - {"hpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER21, - {"hpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER22, - {"hpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER23, - {"hpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER24, - {"hpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER25, - {"hpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER26, - {"hpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER27, - {"hpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER28, - {"hpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER29, - {"hpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER30, - {"hpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER31, - {"hpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32)}}, + {"hpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_CYCLEH, - {"cycleh", MISCREG_CYCLEH, rvTypeFlags(RV32)}}, + {"cycleh", MISCREG_CYCLEH, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_TIMEH, - {"timeh", MISCREG_TIMEH, rvTypeFlags(RV32)}}, + {"timeh", MISCREG_TIMEH, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_INSTRETH, - {"instreth", MISCREG_INSTRETH, rvTypeFlags(RV32)}}, + {"instreth", MISCREG_INSTRETH, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_HPMCOUNTER03H, - {"hpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32)}}, + {"hpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER04H, - {"hpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32)}}, + {"hpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER05H, - {"hpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32)}}, + {"hpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER06H, - {"hpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32)}}, + {"hpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER07H, - {"hpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32)}}, + {"hpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER08H, - {"hpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32)}}, + {"hpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER09H, - {"hpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32)}}, + {"hpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER10H, - {"hpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32)}}, + {"hpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER11H, - {"hpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32)}}, + {"hpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER12H, - {"hpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32)}}, + {"hpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER13H, - {"hpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32)}}, + {"hpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER14H, - {"hpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32)}}, + {"hpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER15H, - {"hpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32)}}, + {"hpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER16H, - {"hpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32)}}, + {"hpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER17H, - {"hpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32)}}, + {"hpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER18H, - {"hpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32)}}, + {"hpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER19H, - {"hpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32)}}, + {"hpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER20H, - {"hpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32)}}, + {"hpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER21H, - {"hpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32)}}, + {"hpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER22H, - {"hpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32)}}, + {"hpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER23H, - {"hpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32)}}, + {"hpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER24H, - {"hpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32)}}, + {"hpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER25H, - {"hpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32)}}, + {"hpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER26H, - {"hpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32)}}, + {"hpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER27H, - {"hpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32)}}, + {"hpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER28H, - {"hpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32)}}, + {"hpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER29H, - {"hpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32)}}, + {"hpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER30H, - {"hpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32)}}, + {"hpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_HPMCOUNTER31H, - {"hpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32)}}, + {"hpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_SSTATUS, - {"sstatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32)}}, + {"sstatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32), + isaExtsFlags('s')}}, {CSR_SEDELEG, - {"sedeleg", MISCREG_SEDELEG, rvTypeFlags(RV64, RV32)}}, + {"sedeleg", MISCREG_SEDELEG, rvTypeFlags(RV64, RV32), + isaExtsFlags('s')}}, {CSR_SIDELEG, - {"sideleg", MISCREG_SIDELEG, rvTypeFlags(RV64, RV32)}}, + {"sideleg", MISCREG_SIDELEG, rvTypeFlags(RV64, RV32), + isaExtsFlags('s')}}, {CSR_SIE, - {"sie", MISCREG_IE, rvTypeFlags(RV64, RV32)}}, + {"sie", MISCREG_IE, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}}, {CSR_STVEC, - {"stvec", MISCREG_STVEC, rvTypeFlags(RV64, RV32)}}, + {"stvec", MISCREG_STVEC, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}}, {CSR_SCOUNTEREN, - {"scounteren", MISCREG_SCOUNTEREN, rvTypeFlags(RV64, RV32)}}, + {"scounteren", MISCREG_SCOUNTEREN, rvTypeFlags(RV64, RV32), + isaExtsFlags('s')}}, {CSR_SSCRATCH, - {"sscratch", MISCREG_SSCRATCH, rvTypeFlags(RV64, RV32)}}, + {"sscratch", MISCREG_SSCRATCH, rvTypeFlags(RV64, RV32), + isaExtsFlags('s')}}, {CSR_SEPC, - {"sepc", MISCREG_SEPC, rvTypeFlags(RV64, RV32)}}, + {"sepc", MISCREG_SEPC, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}}, {CSR_SCAUSE, - {"scause", MISCREG_SCAUSE, rvTypeFlags(RV64, RV32)}}, + {"scause", MISCREG_SCAUSE, rvTypeFlags(RV64, RV32), + isaExtsFlags('s')}}, {CSR_STVAL, - {"stval", MISCREG_STVAL, rvTypeFlags(RV64, RV32)}}, + {"stval", MISCREG_STVAL, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}}, {CSR_SIP, - {"sip", MISCREG_IP, rvTypeFlags(RV64, RV32)}}, + {"sip", MISCREG_IP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}}, {CSR_SATP, - {"satp", MISCREG_SATP, rvTypeFlags(RV64, RV32)}}, + {"satp", MISCREG_SATP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}}, {CSR_MVENDORID, - {"mvendorid", MISCREG_VENDORID, rvTypeFlags(RV64, RV32)}}, + {"mvendorid", MISCREG_VENDORID, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MARCHID, - {"marchid", MISCREG_ARCHID, rvTypeFlags(RV64, RV32)}}, + {"marchid", MISCREG_ARCHID, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MIMPID, - {"mimpid", MISCREG_IMPID, rvTypeFlags(RV64, RV32)}}, + {"mimpid", MISCREG_IMPID, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MHARTID, - {"mhartid", MISCREG_HARTID, rvTypeFlags(RV64, RV32)}}, + {"mhartid", MISCREG_HARTID, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MSTATUS, - {"mstatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32)}}, + {"mstatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MISA, - {"misa", MISCREG_ISA, rvTypeFlags(RV64, RV32)}}, + {"misa", MISCREG_ISA, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MEDELEG, - {"medeleg", MISCREG_MEDELEG, rvTypeFlags(RV64, RV32)}}, + {"medeleg", MISCREG_MEDELEG, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MIDELEG, - {"mideleg", MISCREG_MIDELEG, rvTypeFlags(RV64, RV32)}}, + {"mideleg", MISCREG_MIDELEG, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MIE, - {"mie", MISCREG_IE, rvTypeFlags(RV64, RV32)}}, + {"mie", MISCREG_IE, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MTVEC, - {"mtvec", MISCREG_MTVEC, rvTypeFlags(RV64, RV32)}}, + {"mtvec", MISCREG_MTVEC, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MCOUNTEREN, - {"mcounteren", MISCREG_MCOUNTEREN, rvTypeFlags(RV64, RV32)}}, + {"mcounteren", MISCREG_MCOUNTEREN, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MSTATUSH, - {"mstatush", MISCREG_MSTATUSH, rvTypeFlags(RV32)}}, + {"mstatush", MISCREG_MSTATUSH, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_MSCRATCH, - {"mscratch", MISCREG_MSCRATCH, rvTypeFlags(RV64, RV32)}}, + {"mscratch", MISCREG_MSCRATCH, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MEPC, - {"mepc", MISCREG_MEPC, rvTypeFlags(RV64, RV32)}}, + {"mepc", MISCREG_MEPC, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MCAUSE, - {"mcause", MISCREG_MCAUSE, rvTypeFlags(RV64, RV32)}}, + {"mcause", MISCREG_MCAUSE, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MTVAL, - {"mtval", MISCREG_MTVAL, rvTypeFlags(RV64, RV32)}}, + {"mtval", MISCREG_MTVAL, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MIP, - {"mip", MISCREG_IP, rvTypeFlags(RV64, RV32)}}, + {"mip", MISCREG_IP, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_PMPCFG0, - {"pmpcfg0", MISCREG_PMPCFG0, rvTypeFlags(RV64, RV32)}}, + {"pmpcfg0", MISCREG_PMPCFG0, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, // pmpcfg1 rv32 only {CSR_PMPCFG1, - {"pmpcfg1", MISCREG_PMPCFG1, rvTypeFlags(RV32)}}, + {"pmpcfg1", MISCREG_PMPCFG1, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_PMPCFG2, - {"pmpcfg2", MISCREG_PMPCFG2, rvTypeFlags(RV64, RV32)}}, + {"pmpcfg2", MISCREG_PMPCFG2, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, // pmpcfg3 rv32 only {CSR_PMPCFG3, - {"pmpcfg3", MISCREG_PMPCFG3, rvTypeFlags(RV32)}}, + {"pmpcfg3", MISCREG_PMPCFG3, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_PMPADDR00, - {"pmpaddr0", MISCREG_PMPADDR00, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr0", MISCREG_PMPADDR00, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR01, - {"pmpaddr1", MISCREG_PMPADDR01, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr1", MISCREG_PMPADDR01, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR02, - {"pmpaddr2", MISCREG_PMPADDR02, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr2", MISCREG_PMPADDR02, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR03, - {"pmpaddr3", MISCREG_PMPADDR03, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr3", MISCREG_PMPADDR03, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR04, - {"pmpaddr4", MISCREG_PMPADDR04, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr4", MISCREG_PMPADDR04, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR05, - {"pmpaddr5", MISCREG_PMPADDR05, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr5", MISCREG_PMPADDR05, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR06, - {"pmpaddr6", MISCREG_PMPADDR06, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr6", MISCREG_PMPADDR06, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR07, - {"pmpaddr7", MISCREG_PMPADDR07, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr7", MISCREG_PMPADDR07, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR08, - {"pmpaddr8", MISCREG_PMPADDR08, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr8", MISCREG_PMPADDR08, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR09, - {"pmpaddr9", MISCREG_PMPADDR09, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr9", MISCREG_PMPADDR09, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR10, - {"pmpaddr10", MISCREG_PMPADDR10, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr10", MISCREG_PMPADDR10, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR11, - {"pmpaddr11", MISCREG_PMPADDR11, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr11", MISCREG_PMPADDR11, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR12, - {"pmpaddr12", MISCREG_PMPADDR12, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr12", MISCREG_PMPADDR12, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR13, - {"pmpaddr13", MISCREG_PMPADDR13, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr13", MISCREG_PMPADDR13, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR14, - {"pmpaddr14", MISCREG_PMPADDR14, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr14", MISCREG_PMPADDR14, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_PMPADDR15, - {"pmpaddr15", MISCREG_PMPADDR15, rvTypeFlags(RV64, RV32)}}, + {"pmpaddr15", MISCREG_PMPADDR15, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MCYCLE, - {"mcycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32)}}, + {"mcycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_MINSTRET, - {"minstret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32)}}, + {"minstret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER03, - {"mhpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER04, - {"mhpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER05, - {"mhpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER06, - {"mhpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER07, - {"mhpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER08, - {"mhpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER09, - {"mhpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER10, - {"mhpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER11, - {"mhpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER12, - {"mhpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER13, - {"mhpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER14, - {"mhpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER15, - {"mhpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER16, - {"mhpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER17, - {"mhpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER18, - {"mhpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER19, - {"mhpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER20, - {"mhpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER21, - {"mhpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER22, - {"mhpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER23, - {"mhpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER24, - {"mhpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER25, - {"mhpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER26, - {"mhpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER27, - {"mhpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER28, - {"mhpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER29, - {"mhpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER30, - {"mhpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER31, - {"mhpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32)}}, + {"mhpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MCYCLEH, - {"mcycleh", MISCREG_CYCLEH, rvTypeFlags(RV32)}}, + {"mcycleh", MISCREG_CYCLEH, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_MINSTRETH, - {"minstreth", MISCREG_INSTRETH, rvTypeFlags(RV32)}}, + {"minstreth", MISCREG_INSTRETH, rvTypeFlags(RV32), isaExtsFlags()}}, {CSR_MHPMCOUNTER03H, - {"mhpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32)}}, + {"mhpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER04H, - {"mhpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32)}}, + {"mhpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER05H, - {"mhpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32)}}, + {"mhpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER06H, - {"mhpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32)}}, + {"mhpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER07H, - {"mhpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32)}}, + {"mhpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER08H, - {"mhpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32)}}, + {"mhpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER09H, - {"mhpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32)}}, + {"mhpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER10H, - {"mhpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32)}}, + {"mhpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER11H, - {"mhpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32)}}, + {"mhpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER12H, - {"mhpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32)}}, + {"mhpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER13H, - {"mhpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32)}}, + {"mhpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER14H, - {"mhpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32)}}, + {"mhpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER15H, - {"mhpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32)}}, + {"mhpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER16H, - {"mhpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32)}}, + {"mhpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER17H, - {"mhpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32)}}, + {"mhpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER18H, - {"mhpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32)}}, + {"mhpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER19H, - {"mhpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32)}}, + {"mhpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER20H, - {"mhpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32)}}, + {"mhpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER21H, - {"mhpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32)}}, + {"mhpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER22H, - {"mhpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32)}}, + {"mhpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER23H, - {"mhpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32)}}, + {"mhpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER24H, - {"mhpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32)}}, + {"mhpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER25H, - {"mhpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32)}}, + {"mhpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER26H, - {"mhpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32)}}, + {"mhpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER27H, - {"mhpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32)}}, + {"mhpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER28H, - {"mhpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32)}}, + {"mhpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER29H, - {"mhpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32)}}, + {"mhpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER30H, - {"mhpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32)}}, + {"mhpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMCOUNTER31H, - {"mhpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32)}}, + {"mhpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT03, - {"mhpmevent03", MISCREG_HPMEVENT03, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent03", MISCREG_HPMEVENT03, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT04, - {"mhpmevent04", MISCREG_HPMEVENT04, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent04", MISCREG_HPMEVENT04, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT05, - {"mhpmevent05", MISCREG_HPMEVENT05, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent05", MISCREG_HPMEVENT05, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT06, - {"mhpmevent06", MISCREG_HPMEVENT06, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent06", MISCREG_HPMEVENT06, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT07, - {"mhpmevent07", MISCREG_HPMEVENT07, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent07", MISCREG_HPMEVENT07, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT08, - {"mhpmevent08", MISCREG_HPMEVENT08, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent08", MISCREG_HPMEVENT08, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT09, - {"mhpmevent09", MISCREG_HPMEVENT09, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent09", MISCREG_HPMEVENT09, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT10, - {"mhpmevent10", MISCREG_HPMEVENT10, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent10", MISCREG_HPMEVENT10, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT11, - {"mhpmevent11", MISCREG_HPMEVENT11, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent11", MISCREG_HPMEVENT11, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT12, - {"mhpmevent12", MISCREG_HPMEVENT12, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent12", MISCREG_HPMEVENT12, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT13, - {"mhpmevent13", MISCREG_HPMEVENT13, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent13", MISCREG_HPMEVENT13, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT14, - {"mhpmevent14", MISCREG_HPMEVENT14, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent14", MISCREG_HPMEVENT14, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT15, - {"mhpmevent15", MISCREG_HPMEVENT15, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent15", MISCREG_HPMEVENT15, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT16, - {"mhpmevent16", MISCREG_HPMEVENT16, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent16", MISCREG_HPMEVENT16, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT17, - {"mhpmevent17", MISCREG_HPMEVENT17, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent17", MISCREG_HPMEVENT17, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT18, - {"mhpmevent18", MISCREG_HPMEVENT18, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent18", MISCREG_HPMEVENT18, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT19, - {"mhpmevent19", MISCREG_HPMEVENT19, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent19", MISCREG_HPMEVENT19, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT20, - {"mhpmevent20", MISCREG_HPMEVENT20, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent20", MISCREG_HPMEVENT20, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT21, - {"mhpmevent21", MISCREG_HPMEVENT21, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent21", MISCREG_HPMEVENT21, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT22, - {"mhpmevent22", MISCREG_HPMEVENT22, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent22", MISCREG_HPMEVENT22, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT23, - {"mhpmevent23", MISCREG_HPMEVENT23, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent23", MISCREG_HPMEVENT23, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT24, - {"mhpmevent24", MISCREG_HPMEVENT24, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent24", MISCREG_HPMEVENT24, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT25, - {"mhpmevent25", MISCREG_HPMEVENT25, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent25", MISCREG_HPMEVENT25, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT26, - {"mhpmevent26", MISCREG_HPMEVENT26, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent26", MISCREG_HPMEVENT26, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT27, - {"mhpmevent27", MISCREG_HPMEVENT27, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent27", MISCREG_HPMEVENT27, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT28, - {"mhpmevent28", MISCREG_HPMEVENT28, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent28", MISCREG_HPMEVENT28, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT29, - {"mhpmevent29", MISCREG_HPMEVENT29, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent29", MISCREG_HPMEVENT29, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT30, - {"mhpmevent30", MISCREG_HPMEVENT30, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent30", MISCREG_HPMEVENT30, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_MHPMEVENT31, - {"mhpmevent31", MISCREG_HPMEVENT31, rvTypeFlags(RV64, RV32)}}, + {"mhpmevent31", MISCREG_HPMEVENT31, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_TSELECT, - {"tselect", MISCREG_TSELECT, rvTypeFlags(RV64, RV32)}}, + {"tselect", MISCREG_TSELECT, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_TDATA1, - {"tdata1", MISCREG_TDATA1, rvTypeFlags(RV64, RV32)}}, + {"tdata1", MISCREG_TDATA1, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_TDATA2, - {"tdata2", MISCREG_TDATA2, rvTypeFlags(RV64, RV32)}}, + {"tdata2", MISCREG_TDATA2, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_TDATA3, - {"tdata3", MISCREG_TDATA3, rvTypeFlags(RV64, RV32)}}, + {"tdata3", MISCREG_TDATA3, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_DCSR, - {"dcsr", MISCREG_DCSR, rvTypeFlags(RV64, RV32)}}, + {"dcsr", MISCREG_DCSR, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_DPC, - {"dpc", MISCREG_DPC, rvTypeFlags(RV64, RV32)}}, + {"dpc", MISCREG_DPC, rvTypeFlags(RV64, RV32), isaExtsFlags()}}, {CSR_DSCRATCH, - {"dscratch", MISCREG_DSCRATCH, rvTypeFlags(RV64, RV32)}}, + {"dscratch", MISCREG_DSCRATCH, rvTypeFlags(RV64, RV32), + isaExtsFlags()}}, {CSR_VSTART, - {"vstart", MISCREG_VSTART, rvTypeFlags(RV64, RV32)}}, + {"vstart", MISCREG_VSTART, rvTypeFlags(RV64, RV32), + isaExtsFlags('v')}}, {CSR_VXSAT, - {"vxsat", MISCREG_VXSAT, rvTypeFlags(RV64, RV32)}}, + {"vxsat", MISCREG_VXSAT, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}}, {CSR_VXRM, - {"vxrm", MISCREG_VXRM, rvTypeFlags(RV64, RV32)}}, + {"vxrm", MISCREG_VXRM, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}}, {CSR_VCSR, - {"vcsr", MISCREG_VCSR, rvTypeFlags(RV64, RV32)}}, + {"vcsr", MISCREG_VCSR, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}}, {CSR_VL, - {"vl", MISCREG_VL, rvTypeFlags(RV64, RV32)}}, + {"vl", MISCREG_VL, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}}, {CSR_VTYPE, - {"vtype", MISCREG_VTYPE, rvTypeFlags(RV64, RV32)}}, + {"vtype", MISCREG_VTYPE, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}}, {CSR_VLENB, - {"VLENB", MISCREG_VLENB, rvTypeFlags(RV64, RV32)}} + {"VLENB", MISCREG_VLENB, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}} }; /** @@ -1118,41 +1305,137 @@ const RegVal STATUS_UPIE_MASK = 1ULL << 4; const RegVal STATUS_MIE_MASK = 1ULL << 3; const RegVal STATUS_SIE_MASK = 1ULL << 1; const RegVal STATUS_UIE_MASK = 1ULL << 0; -const RegVal MSTATUS_MASKS[enums::Num_RiscvType] = { - [RV32] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | STATUS_TW_MASK | - STATUS_TVM_MASK | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_MPRV_MASK | STATUS_XS_MASK | STATUS_FS_MASK | - STATUS_VS_MASK | STATUS_MPP_MASK | STATUS_SPP_MASK | - STATUS_MPIE_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | - STATUS_MIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, - [RV64] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | - STATUS_SBE_MASK[RV64] | STATUS_SXL_MASK | STATUS_UXL_MASK | - STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK | - STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK| - STATUS_MPP_MASK | STATUS_SPP_MASK | STATUS_MPIE_MASK | - STATUS_SPIE_MASK | STATUS_UPIE_MASK | STATUS_MIE_MASK | - STATUS_SIE_MASK | STATUS_UIE_MASK, +const RegVal +MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = STATUS_SD_MASKS[RV32] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK | + STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MNU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK | + STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | + STATUS_MPIE_MASK | STATUS_UPIE_MASK | + STATUS_MIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | + STATUS_TW_MASK | STATUS_TVM_MASK | STATUS_MXR_MASK | + STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | + STATUS_MIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | + STATUS_TW_MASK | STATUS_TVM_MASK | STATUS_MXR_MASK | + STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | + STATUS_UPIE_MASK | STATUS_MIE_MASK | STATUS_SIE_MASK | + STATUS_UIE_MASK, + }, + [RV64] = { + [enums::M] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | + STATUS_UXL_MASK | STATUS_TW_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MNU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | + STATUS_UXL_MASK | STATUS_TW_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | + STATUS_MPIE_MASK | STATUS_UPIE_MASK | + STATUS_MIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = STATUS_SD_MASKS[RV64] | + STATUS_MBE_MASK[RV64] | STATUS_SBE_MASK[RV64] | + STATUS_SXL_MASK | STATUS_UXL_MASK | + STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | + STATUS_MIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV64] | + STATUS_MBE_MASK[RV64] | STATUS_SBE_MASK[RV64] | + STATUS_SXL_MASK | STATUS_UXL_MASK | + STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | + STATUS_MIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, + }, }; // rv32 only -const RegVal MSTATUSH_MASKS = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32]; -const RegVal SSTATUS_MASKS[enums::Num_RiscvType] = { - [RV32] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | - STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | - STATUS_SIE_MASK | STATUS_UIE_MASK, - [RV64] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | STATUS_MXR_MASK | - STATUS_SUM_MASK | STATUS_XS_MASK | STATUS_FS_MASK | - STATUS_VS_MASK | STATUS_SPP_MASK | STATUS_SPIE_MASK | - STATUS_UPIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, +const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet] = { + [enums::M] = STATUS_MBE_MASK[RV32], + [enums::MU] = STATUS_MBE_MASK[RV32], + [enums::MNU] = STATUS_MBE_MASK[RV32], + [enums::MSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32], + [enums::MNSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32], }; -const RegVal USTATUS_MASKS[enums::Num_RiscvType] = { - [RV32] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | - STATUS_UPIE_MASK | STATUS_UIE_MASK, - [RV64] = STATUS_SD_MASKS[RV64] | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | - STATUS_UPIE_MASK | STATUS_UIE_MASK, +const RegVal +SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = 0ULL, + [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | + STATUS_SIE_MASK | STATUS_UIE_MASK, + }, + [RV64] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = 0ULL, + [enums::MSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | + STATUS_UPIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, + }, +}; +const RegVal +USTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = STATUS_SD_MASKS[RV32] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = 0ULL, + [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + }, + [RV64] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = STATUS_SD_MASKS[RV64] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = 0ULL, + [enums::MNSU] = STATUS_SD_MASKS[RV64] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + }, }; const RegVal MEI_MASK = 1ULL << 11; @@ -1164,13 +1447,33 @@ const RegVal UTI_MASK = 1ULL << 4; const RegVal MSI_MASK = 1ULL << 3; const RegVal SSI_MASK = 1ULL << 1; const RegVal USI_MASK = 1ULL << 0; -const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK | - MTI_MASK | STI_MASK | UTI_MASK | - MSI_MASK | SSI_MASK | USI_MASK; -const RegVal SI_MASK = SEI_MASK | UEI_MASK | - STI_MASK | UTI_MASK | - SSI_MASK | USI_MASK; -const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK; +const RegVal MI_MASK[enums::Num_PrivilegeModeSet] = { + [enums::M] = MEI_MASK| MTI_MASK | MSI_MASK, + [enums::MU] = MEI_MASK| MTI_MASK | MSI_MASK, + [enums::MNU] = MEI_MASK | UEI_MASK | MTI_MASK | UTI_MASK | + MSI_MASK | USI_MASK, + [enums::MSU] = MEI_MASK | SEI_MASK | MTI_MASK | STI_MASK | + MSI_MASK | SSI_MASK, + [enums::MNSU] = MEI_MASK | SEI_MASK | UEI_MASK | + MTI_MASK | STI_MASK | UTI_MASK | + MSI_MASK | SSI_MASK | USI_MASK, +}; +const RegVal SI_MASK[enums::Num_PrivilegeModeSet] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = UEI_MASK | UTI_MASK | USI_MASK, + [enums::MSU] = SEI_MASK | STI_MASK | SSI_MASK, + [enums::MNSU] = SEI_MASK | UEI_MASK | + STI_MASK | UTI_MASK | + SSI_MASK | USI_MASK, +}; +const RegVal UI_MASK[enums::Num_PrivilegeModeSet] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = UEI_MASK | UTI_MASK | USI_MASK, + [enums::MSU] = 0ULL, + [enums::MNSU] = UEI_MASK | UTI_MASK | USI_MASK, +}; const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1; const RegVal FRM_MASK = 0x7; @@ -1179,34 +1482,167 @@ const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType] = { [RV64] = (1ULL << 63), }; -const std::unordered_map CSRMasks[enums::Num_RiscvType] = { - [RV32] = {{CSR_USTATUS, USTATUS_MASKS[RV32]}, - {CSR_UIE, UI_MASK}, - {CSR_UIP, UI_MASK}, - {CSR_FFLAGS, FFLAGS_MASK}, - {CSR_FRM, FRM_MASK}, - {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, - {CSR_SSTATUS, SSTATUS_MASKS[RV32]}, - {CSR_SIE, SI_MASK}, - {CSR_SIP, SI_MASK}, - {CSR_MSTATUS, MSTATUS_MASKS[RV32]}, - {CSR_MISA, MISA_MASKS[RV32]}, - {CSR_MIE, MI_MASK}, - {CSR_MSTATUSH, MSTATUSH_MASKS}, - {CSR_MIP, MI_MASK}}, - [RV64] = {{CSR_USTATUS, USTATUS_MASKS[RV64]}, - {CSR_UIE, UI_MASK}, - {CSR_UIP, UI_MASK}, - {CSR_FFLAGS, FFLAGS_MASK}, - {CSR_FRM, FRM_MASK}, - {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, - {CSR_SSTATUS, SSTATUS_MASKS[RV64]}, - {CSR_SIE, SI_MASK}, - {CSR_SIP, SI_MASK}, - {CSR_MSTATUS, MSTATUS_MASKS[RV64]}, - {CSR_MISA, MISA_MASKS[RV64]}, - {CSR_MIE, MI_MASK}, - {CSR_MIP, MI_MASK}}, +const std::unordered_map +CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::M]}, + {CSR_UIE, UI_MASK[enums::M]}, + {CSR_UIP, UI_MASK[enums::M]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::M]}, + {CSR_SIE, SI_MASK[enums::M]}, + {CSR_SIP, SI_MASK[enums::M]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::M]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::M]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::M]}, + {CSR_MIP, MI_MASK[enums::M]}, + }, + [enums::MU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MU]}, + {CSR_UIE, UI_MASK[enums::MU]}, + {CSR_UIP, UI_MASK[enums::MU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MU]}, + {CSR_SIE, SI_MASK[enums::MU]}, + {CSR_SIP, SI_MASK[enums::MU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MU]}, + {CSR_MIP, MI_MASK[enums::MU]}, + }, + [enums::MNU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MNU]}, + {CSR_UIE, UI_MASK[enums::MNU]}, + {CSR_UIP, UI_MASK[enums::MNU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MNU]}, + {CSR_SIE, SI_MASK[enums::MNU]}, + {CSR_SIP, SI_MASK[enums::MNU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MNU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MNU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MNU]}, + {CSR_MIP, MI_MASK[enums::MNU]}, + }, + [enums::MSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MSU]}, + {CSR_UIE, UI_MASK[enums::MSU]}, + {CSR_UIP, UI_MASK[enums::MSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MSU]}, + {CSR_SIE, SI_MASK[enums::MSU]}, + {CSR_SIP, SI_MASK[enums::MSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MSU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MSU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MSU]}, + {CSR_MIP, MI_MASK[enums::MSU]}, + }, + [enums::MNSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MNSU]}, + {CSR_UIE, UI_MASK[enums::MNSU]}, + {CSR_UIP, UI_MASK[enums::MNSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MNSU]}, + {CSR_SIE, SI_MASK[enums::MNSU]}, + {CSR_SIP, SI_MASK[enums::MNSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MNSU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MNSU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MNSU]}, + {CSR_MIP, MI_MASK[enums::MNSU]}, + }, + }, + [RV64] = { + [enums::M] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::M]}, + {CSR_UIE, UI_MASK[enums::M]}, + {CSR_UIP, UI_MASK[enums::M]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::M]}, + {CSR_SIE, SI_MASK[enums::M]}, + {CSR_SIP, SI_MASK[enums::M]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::M]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::M]}, + {CSR_MIP, MI_MASK[enums::M]}, + }, + [enums::MU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MU]}, + {CSR_UIE, UI_MASK[enums::MU]}, + {CSR_UIP, UI_MASK[enums::MU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MU]}, + {CSR_SIE, SI_MASK[enums::MU]}, + {CSR_SIP, SI_MASK[enums::MU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MU]}, + {CSR_MIP, MI_MASK[enums::MU]}, + }, + [enums::MNU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MNU]}, + {CSR_UIE, UI_MASK[enums::MNU]}, + {CSR_UIP, UI_MASK[enums::MNU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MNU]}, + {CSR_SIE, SI_MASK[enums::MNU]}, + {CSR_SIP, SI_MASK[enums::MNU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MNU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MNU]}, + {CSR_MIP, MI_MASK[enums::MNU]}, + }, + [enums::MSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MSU]}, + {CSR_UIE, UI_MASK[enums::MSU]}, + {CSR_UIP, UI_MASK[enums::MSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MSU]}, + {CSR_SIE, SI_MASK[enums::MSU]}, + {CSR_SIP, SI_MASK[enums::MSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MSU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MSU]}, + {CSR_MIP, MI_MASK[enums::MSU]}, + }, + [enums::MNSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MNSU]}, + {CSR_UIE, UI_MASK[enums::MNSU]}, + {CSR_UIP, UI_MASK[enums::MNSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MNSU]}, + {CSR_SIE, SI_MASK[enums::MNSU]}, + {CSR_SIP, SI_MASK[enums::MNSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MNSU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MNSU]}, + {CSR_MIP, MI_MASK[enums::MNSU]}, + }, + }, }; } // namespace RiscvISA diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 48ce1d5d3b..661fe2e2ca 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -167,13 +167,22 @@ getRvType(ThreadContext* tc) return isa->rvType(); } +static PrivilegeModeSet +getPrivilegeModeSet(ThreadContext* tc) +{ + auto isa = dynamic_cast(tc->getIsaPtr()); + panic_if(!isa, "Cannot derive rv_type from non-riscv isa"); + return isa->getPrivilegeModeSet(); +} + template static void setRegNoEffectWithMask( - ThreadContext *context, RiscvType type, CSRIndex idx, xint val) + ThreadContext *context, RiscvType type, PrivilegeModeSet pms, + CSRIndex idx, xint val) { RegVal oldVal, newVal; - RegVal mask = CSRMasks[type].at(idx); + RegVal mask = CSRMasks[type][pms].at(idx); oldVal = context->readMiscRegNoEffect(CSRData.at(idx).physIndex); newVal = (oldVal & ~mask) | (val & mask); context->setMiscRegNoEffect(CSRData.at(idx).physIndex, newVal); @@ -181,10 +190,12 @@ setRegNoEffectWithMask( template static void -setRegWithMask(ThreadContext *context, RiscvType type, CSRIndex idx, xint val) +setRegWithMask( + ThreadContext *context, RiscvType type, PrivilegeModeSet pms, + CSRIndex idx, xint val) { RegVal oldVal, newVal; - RegVal mask = CSRMasks[type].at(idx); + RegVal mask = CSRMasks[type][pms].at(idx); oldVal = context->readMiscReg(CSRData.at(idx).physIndex); newVal = (oldVal & ~mask) | (val & mask); context->setMiscReg(CSRData.at(idx).physIndex, newVal); @@ -207,7 +218,8 @@ RemoteGDB::acc(Addr va, size_t len) PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read); SATP satp = context()->readMiscReg(MISCREG_SATP); - if (pmode != PrivilegeMode::PRV_M && + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); + if (misa.rvs && pmode != PrivilegeMode::PRV_M && satp.mode != AddrXlateMode::BARE) { Walker *walker = mmu->getDataWalker(); Fault fault = walker->startFunctional( @@ -225,7 +237,8 @@ void RemoteGDB::Riscv32GdbRegCache::getRegs(ThreadContext *context) { DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size()); - auto& RVxCSRMasks = CSRMasks[RV32]; + PrivilegeModeSet pms = getPrivilegeModeSet(context); + auto& RVxCSRMasks = CSRMasks[RV32][pms]; // General registers for (int i = 0; i < int_reg::NumArchRegs; i++) { @@ -339,6 +352,7 @@ void RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const { DPRINTF(GDBAcc, "setregs in remotegdb \n"); + PrivilegeModeSet pms = getPrivilegeModeSet(context); for (int i = 0; i < int_reg::NumArchRegs; i++) context->setReg(intRegClass[i], r.gpr[i]); context->pcState(r.pc); @@ -347,16 +361,16 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const for (int i = 0; i < float_reg::NumRegs; i++) context->setReg(floatRegClass[i], r.fpu[i]); - setRegNoEffectWithMask(context, RV32, CSR_FFLAGS, r.fflags); - setRegNoEffectWithMask(context, RV32, CSR_FRM, r.frm); - setRegNoEffectWithMask(context, RV32, CSR_FCSR, r.fcsr); + setRegNoEffectWithMask(context, RV32, pms, CSR_FFLAGS, r.fflags); + setRegNoEffectWithMask(context, RV32, pms, CSR_FRM, r.frm); + setRegNoEffectWithMask(context, RV32, pms, CSR_FCSR, r.fcsr); // TODO: implement CSR counter registers for mcycle(h), minstret(h) // U mode CSR - setRegNoEffectWithMask(context, RV32, CSR_USTATUS, r.ustatus); - setRegWithMask(context, RV32, CSR_UIE, r.uie); - setRegWithMask(context, RV32, CSR_UIP, r.uip); + setRegNoEffectWithMask(context, RV32, pms, CSR_USTATUS, r.ustatus); + setRegWithMask(context, RV32, pms, CSR_UIE, r.uie); + setRegWithMask(context, RV32, pms, CSR_UIP, r.uip); context->setMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex, r.utvec); context->setMiscRegNoEffect( @@ -369,9 +383,9 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_UTVAL).physIndex, r.utval); // S mode CSR - setRegNoEffectWithMask(context, RV32, CSR_SSTATUS, r.sstatus); - setRegWithMask(context, RV32, CSR_SIE, r.sie); - setRegWithMask(context, RV32, CSR_SIP, r.sip); + setRegNoEffectWithMask(context, RV32, pms, CSR_SSTATUS, r.sstatus); + setRegWithMask(context, RV32, pms, CSR_SIE, r.sie); + setRegWithMask(context, RV32, pms, CSR_SIP, r.sip); context->setMiscRegNoEffect( CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg); context->setMiscRegNoEffect( @@ -392,10 +406,10 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_SATP).physIndex, r.satp); // M mode CSR - setRegNoEffectWithMask(context, RV32, CSR_MSTATUS, r.mstatus); - setRegNoEffectWithMask(context, RV32, CSR_MISA, r.misa); - setRegWithMask(context, RV32, CSR_MIE, r.mie); - setRegWithMask(context, RV32, CSR_MIP, r.mip); + setRegNoEffectWithMask(context, RV32, pms, CSR_MSTATUS, r.mstatus); + setRegNoEffectWithMask(context, RV32, pms, CSR_MISA, r.misa); + setRegWithMask(context, RV32, pms, CSR_MIE, r.mie); + setRegWithMask(context, RV32, pms, CSR_MIP, r.mip); context->setMiscRegNoEffect( CSRData.at(CSR_MEDELEG).physIndex, r.medeleg); context->setMiscRegNoEffect( @@ -420,7 +434,8 @@ void RemoteGDB::Riscv64GdbRegCache::getRegs(ThreadContext *context) { DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size()); - auto& RVxCSRMasks = CSRMasks[RV64]; + PrivilegeModeSet pms = getPrivilegeModeSet(context); + auto& RVxCSRMasks = CSRMasks[RV64][pms]; // General registers for (int i = 0; i < int_reg::NumArchRegs; i++) { @@ -528,6 +543,7 @@ void RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const { DPRINTF(GDBAcc, "setregs in remotegdb \n"); + PrivilegeModeSet pms = getPrivilegeModeSet(context); for (int i = 0; i < int_reg::NumArchRegs; i++) context->setReg(intRegClass[i], r.gpr[i]); context->pcState(r.pc); @@ -536,16 +552,16 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const for (int i = 0; i < float_reg::NumRegs; i++) context->setReg(floatRegClass[i], r.fpu[i]); - setRegNoEffectWithMask(context, RV64, CSR_FFLAGS, r.fflags); - setRegNoEffectWithMask(context, RV64, CSR_FRM, r.frm); - setRegNoEffectWithMask(context, RV64, CSR_FCSR, r.fcsr); + setRegNoEffectWithMask(context, RV64, pms, CSR_FFLAGS, r.fflags); + setRegNoEffectWithMask(context, RV64, pms, CSR_FRM, r.frm); + setRegNoEffectWithMask(context, RV64, pms, CSR_FCSR, r.fcsr); // TODO: implement CSR counter registers for mcycle, minstret // U mode CSR - setRegNoEffectWithMask(context, RV64, CSR_USTATUS, r.ustatus); - setRegWithMask(context, RV64, CSR_UIE, r.uie); - setRegWithMask(context, RV64, CSR_UIP, r.uip); + setRegNoEffectWithMask(context, RV64, pms, CSR_USTATUS, r.ustatus); + setRegWithMask(context, RV64, pms, CSR_UIE, r.uie); + setRegWithMask(context, RV64, pms, CSR_UIP, r.uip); context->setMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex, r.utvec); context->setMiscRegNoEffect( @@ -558,9 +574,10 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_UTVAL).physIndex, r.utval); // S mode CSR - setRegNoEffectWithMask(context, RV64, CSR_SSTATUS, r.sstatus); - setRegWithMask(context, RV64, CSR_SIE, r.sie); - setRegWithMask(context, RV64, CSR_SIP, r.sip); + setRegNoEffectWithMask( + context, RV64, pms, CSR_SSTATUS, r.sstatus); + setRegWithMask(context, RV64, pms, CSR_SIE, r.sie); + setRegWithMask(context, RV64, pms, CSR_SIP, r.sip); context->setMiscRegNoEffect( CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg); context->setMiscRegNoEffect( @@ -581,10 +598,11 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_SATP).physIndex, r.satp); // M mode CSR - setRegNoEffectWithMask(context, RV64, CSR_MSTATUS, r.mstatus); - setRegNoEffectWithMask(context, RV64, CSR_MISA, r.misa); - setRegWithMask(context, RV64, CSR_MIE, r.mie); - setRegWithMask(context, RV64, CSR_MIP, r.mip); + setRegNoEffectWithMask( + context, RV64, pms, CSR_MSTATUS, r.mstatus); + setRegNoEffectWithMask(context, RV64, pms, CSR_MISA, r.misa); + setRegWithMask(context, RV64, pms, CSR_MIE, r.mie); + setRegWithMask(context, RV64, pms, CSR_MIP, r.mip); context->setMiscRegNoEffect( CSRData.at(CSR_MEDELEG).physIndex, r.medeleg); context->setMiscRegNoEffect( diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc index 69317188f8..679806ec8c 100644 --- a/src/arch/riscv/tlb.cc +++ b/src/arch/riscv/tlb.cc @@ -341,9 +341,12 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc, if (FullSystem) { PrivilegeMode pmode = getMemPriv(tc, mode); + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); SATP satp = tc->readMiscReg(MISCREG_SATP); - if (pmode == PrivilegeMode::PRV_M || satp.mode == AddrXlateMode::BARE) + if (!misa.rvs || pmode == PrivilegeMode::PRV_M || + satp.mode == AddrXlateMode::BARE) { req->setFlags(Request::PHYSICAL); + } Fault fault; if (req->getFlags() & Request::PHYSICAL) { @@ -434,8 +437,9 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, MMU *mmu = static_cast(tc->getMMUPtr()); PrivilegeMode pmode = mmu->getMemPriv(tc, mode); + MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA); SATP satp = tc->readMiscReg(MISCREG_SATP); - if (pmode != PrivilegeMode::PRV_M && + if (misa.rvs && pmode != PrivilegeMode::PRV_M && satp.mode != AddrXlateMode::BARE) { Walker *walker = mmu->getDataWalker(); unsigned logBytes;