diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 29acbbcea2..d32cbff8f6 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -70,8 +70,6 @@ class ArmMMU(BaseMMU):
     itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)
     dtb = ArmTLB(entry_type="data", next_level=Parent.l2_shared)
 
-    sys = Param.System(Parent.any, "system object parameter")
-
     stage2_itb = Param.ArmTLB(
         ArmStage2TLB(entry_type="instruction"),
         "Stage 2 Instruction TLB")