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arch,cpu: Turn (read|set)*Reg into inline helpers.

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Eliminate readFloatRegFlat and setFloatRegFlat for the Fast Model
ThreadContext since ARM doesn't use those register types, and those
methods are no longer required by the ThreadContext interface.

Change-Id: Ic149c64e2fbf1d313066fefe480c435eef6d66e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49113
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-06 05:04:08 -07:00
parent a9ef634fa8
commit a19bb5f5ab
15 changed files with 356 additions and 1366 deletions
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188
src/cpu/thread_context.hh
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@@ -200,36 +200,91 @@ class ThreadContext : public PCEventScope
virtual void setReg(const RegId &reg, RegVal val);
virtual void setReg(const RegId &reg, const void *val);
virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
RegVal
readIntReg(RegIndex reg_idx) const
{
return getReg(RegId(IntRegClass, reg_idx));
}
virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
RegVal
readFloatReg(RegIndex reg_idx) const
{
return getReg(RegId(FloatRegClass, reg_idx));
}
virtual const TheISA::VecRegContainer&
readVecReg(const RegId& reg) const = 0;
virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
TheISA::VecRegContainer
readVecReg(const RegId &reg) const
{
TheISA::VecRegContainer val;
getReg(reg, &val);
return val;
}
TheISA::VecRegContainer&
getWritableVecReg(const RegId& reg)
{
return *(TheISA::VecRegContainer *)getWritableReg(reg);
}
virtual RegVal readVecElem(const RegId& reg) const = 0;
RegVal
readVecElem(const RegId& reg) const
{
return getReg(reg);
}
virtual const TheISA::VecPredRegContainer& readVecPredReg(
const RegId& reg) const = 0;
virtual TheISA::VecPredRegContainer& getWritableVecPredReg(
const RegId& reg) = 0;
TheISA::VecPredRegContainer
readVecPredReg(const RegId &reg) const
{
TheISA::VecPredRegContainer val;
getReg(reg, &val);
return val;
}
TheISA::VecPredRegContainer&
getWritableVecPredReg(const RegId& reg)
{
return *(TheISA::VecPredRegContainer *)getWritableReg(reg);
}
virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
RegVal
readCCReg(RegIndex reg_idx) const
{
return getReg(RegId(CCRegClass, reg_idx));
}
virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
void
setIntReg(RegIndex reg_idx, RegVal val)
{
setReg(RegId(IntRegClass, reg_idx), val);
}
virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
void
setFloatReg(RegIndex reg_idx, RegVal val)
{
setReg(RegId(FloatRegClass, reg_idx), val);
}
virtual void setVecReg(const RegId& reg,
const TheISA::VecRegContainer& val) = 0;
void
setVecReg(const RegId& reg, const TheISA::VecRegContainer &val)
{
setReg(reg, &val);
}
virtual void setVecElem(const RegId& reg, RegVal val) = 0;
void
setVecElem(const RegId& reg, RegVal val)
{
setReg(reg, val);
}
virtual void setVecPredReg(const RegId& reg,
const TheISA::VecPredRegContainer& val) = 0;
void
setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val)
{
setReg(reg, &val);
}
virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
void
setCCReg(RegIndex reg_idx, RegVal val)
{
setReg(RegId(CCRegClass, reg_idx), val);
}
virtual const PCStateBase &pcState() const = 0;
@@ -286,30 +341,87 @@ class ThreadContext : public PCEventScope
virtual void setRegFlat(const RegId &reg, RegVal val);
virtual void setRegFlat(const RegId &reg, const void *val);
virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
RegVal
readIntRegFlat(RegIndex idx) const
{
return getRegFlat(RegId(IntRegClass, idx));
}
void
setIntRegFlat(RegIndex idx, RegVal val)
{
setRegFlat(RegId(IntRegClass, idx), val);
}
virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
RegVal
readFloatRegFlat(RegIndex idx) const
{
return getRegFlat(RegId(FloatRegClass, idx));
}
void
setFloatRegFlat(RegIndex idx, RegVal val)
{
setRegFlat(RegId(FloatRegClass, idx), val);
}
virtual const TheISA::VecRegContainer&
readVecRegFlat(RegIndex idx) const = 0;
virtual TheISA::VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
virtual void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) = 0;
TheISA::VecRegContainer
readVecRegFlat(RegIndex idx) const
{
TheISA::VecRegContainer val;
getRegFlat(RegId(VecRegClass, idx), &val);
return val;
}
TheISA::VecRegContainer&
getWritableVecRegFlat(RegIndex idx)
{
return *(TheISA::VecRegContainer *)
getWritableRegFlat(RegId(VecRegClass, idx));
}
void
setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer& val)
{
setRegFlat(RegId(VecRegClass, idx), &val);
}
virtual RegVal readVecElemFlat(RegIndex idx) const = 0;
virtual void setVecElemFlat(RegIndex idx, RegVal val) = 0;
RegVal
readVecElemFlat(RegIndex idx) const
{
return getRegFlat(RegId(VecElemClass, idx));
}
void
setVecElemFlat(RegIndex idx, RegVal val)
{
setRegFlat(RegId(VecElemClass, idx), val);
}
virtual const TheISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const = 0;
virtual TheISA::VecPredRegContainer& getWritableVecPredRegFlat(
RegIndex idx) = 0;
virtual void setVecPredRegFlat(RegIndex idx,
const TheISA::VecPredRegContainer& val) = 0;
TheISA::VecPredRegContainer
readVecPredRegFlat(RegIndex idx) const
{
TheISA::VecPredRegContainer val;
getRegFlat(RegId(VecPredRegClass, idx), &val);
return val;
}
TheISA::VecPredRegContainer&
getWritableVecPredRegFlat(RegIndex idx)
{
return *(TheISA::VecPredRegContainer *)getWritableRegFlat(
RegId(VecPredRegClass, idx));
}
void
setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer& val)
{
setRegFlat(RegId(VecPredRegClass, idx), &val);
}
virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
RegVal
readCCRegFlat(RegIndex idx) const
{
return getRegFlat(RegId(CCRegClass, idx));
}
void
setCCRegFlat(RegIndex idx, RegVal val)
{
setRegFlat(RegId(CCRegClass, idx), val);
}
/** @} */
// hardware transactional memory