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arch,cpu: Turn (read|set)*Reg into inline helpers.

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Eliminate readFloatRegFlat and setFloatRegFlat for the Fast Model
ThreadContext since ARM doesn't use those register types, and those
methods are no longer required by the ThreadContext interface.

Change-Id: Ic149c64e2fbf1d313066fefe480c435eef6d66e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49113
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-06 05:04:08 -07:00
parent a9ef634fa8
commit a19bb5f5ab
15 changed files with 356 additions and 1366 deletions
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8
src/arch/arm/fastmodel/iris/thread_context.cc
View File

@@ -718,9 +718,6 @@ ThreadContext::getRegFlat(const RegId &reg, void *val) const
case IntRegClass:
*(RegVal *)val = readIntRegFlat(idx);
break;
case FloatRegClass:
*(RegVal *)val = readFloatRegFlat(idx);
break;
case VecRegClass:
*(ArmISA::VecRegContainer *)val = readVecRegFlat(idx);
break;
@@ -749,9 +746,6 @@ ThreadContext::setRegFlat(const RegId &reg, const void *val)
case IntRegClass:
setIntRegFlat(idx, *(RegVal *)val);
break;
case FloatRegClass:
setFloatRegFlat(idx, *(RegVal *)val);
break;
case VecRegClass:
setVecRegFlat(idx, *(ArmISA::VecRegContainer *)val);
break;
@@ -916,7 +910,7 @@ ThreadContext::readVecPredReg(const RegId &reg_id) const
return reg;
}
const ArmISA::VecPredRegContainer &
ArmISA::VecPredRegContainer
ThreadContext::readVecPredRegFlat(RegIndex idx) const
{
return readVecPredReg(RegId(VecPredRegClass, idx));

102
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -286,70 +286,58 @@ class ThreadContext : public gem5::ThreadContext
void setReg(const RegId &reg, RegVal val) override;
void setReg(const RegId &reg, const void *val) override;
RegVal readIntReg(RegIndex reg_idx) const override;
virtual RegVal readIntReg(RegIndex reg_idx) const;
RegVal
readFloatReg(RegIndex reg_idx) const override
virtual const ArmISA::VecRegContainer &readVecReg(const RegId &reg) const;
virtual ArmISA::VecRegContainer &
getWritableVecReg(const RegId &reg)
{
panic("%s not implemented.", __FUNCTION__);
}
const ArmISA::VecRegContainer &readVecReg(const RegId &reg) const override;
ArmISA::VecRegContainer &
getWritableVecReg(const RegId &reg) override
virtual RegVal
readVecElem(const RegId &reg) const
{
panic("%s not implemented.", __FUNCTION__);
}
RegVal
readVecElem(const RegId &reg) const override
virtual const ArmISA::VecPredRegContainer &
readVecPredReg(const RegId &reg) const;
virtual ArmISA::VecPredRegContainer &
getWritableVecPredReg(const RegId &reg)
{
panic("%s not implemented.", __FUNCTION__);
}
const ArmISA::VecPredRegContainer &
readVecPredReg(const RegId &reg) const override;
ArmISA::VecPredRegContainer &
getWritableVecPredReg(const RegId &reg) override
{
panic("%s not implemented.", __FUNCTION__);
}
RegVal
readCCReg(RegIndex reg_idx) const override
virtual RegVal
readCCReg(RegIndex reg_idx) const
{
return readCCRegFlat(reg_idx);
}
void setIntReg(RegIndex reg_idx, RegVal val) override;
virtual void setIntReg(RegIndex reg_idx, RegVal val);
void
setFloatReg(RegIndex reg_idx, RegVal val) override
virtual void
setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val)
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val) override
virtual void
setVecElem(const RegId& reg, RegVal val)
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecElem(const RegId& reg, RegVal val) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
virtual void
setVecPredReg(const RegId &reg,
const ArmISA::VecPredRegContainer &val) override
const ArmISA::VecPredRegContainer &val)
{
panic("%s not implemented.", __FUNCTION__);
}
void
setCCReg(RegIndex reg_idx, RegVal val) override
virtual void
setCCReg(RegIndex reg_idx, RegVal val)
{
setCCRegFlat(reg_idx, val);
}
@@ -412,59 +400,47 @@ class ThreadContext : public gem5::ThreadContext
void setRegFlat(const RegId &reg, RegVal val) override;
void setRegFlat(const RegId &reg, const void *val) override;
RegVal readIntRegFlat(RegIndex idx) const override;
void setIntRegFlat(RegIndex idx, uint64_t val) override;
virtual RegVal readIntRegFlat(RegIndex idx) const;
virtual void setIntRegFlat(RegIndex idx, uint64_t val);
RegVal
readFloatRegFlat(RegIndex idx) const override
virtual const ArmISA::VecRegContainer &readVecRegFlat(RegIndex idx) const;
virtual ArmISA::VecRegContainer &
getWritableVecRegFlat(RegIndex idx)
{
panic("%s not implemented.", __FUNCTION__);
}
void
setFloatRegFlat(RegIndex idx, RegVal val) override
virtual void
setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val)
{
panic("%s not implemented.", __FUNCTION__);
}
const ArmISA::VecRegContainer &readVecRegFlat(RegIndex idx) const override;
ArmISA::VecRegContainer &
getWritableVecRegFlat(RegIndex idx) override
virtual RegVal
readVecElemFlat(RegIndex idx) const
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val) override
virtual void
setVecElemFlat(RegIndex idx, RegVal val)
{
panic("%s not implemented.", __FUNCTION__);
}
RegVal
readVecElemFlat(RegIndex idx) const override
virtual ArmISA::VecPredRegContainer readVecPredRegFlat(RegIndex idx) const;
virtual ArmISA::VecPredRegContainer &
getWritableVecPredRegFlat(RegIndex idx)
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecElemFlat(RegIndex idx, RegVal val) override
{
panic("%s not implemented.", __FUNCTION__);
}
const ArmISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const override;
ArmISA::VecPredRegContainer &
getWritableVecPredRegFlat(RegIndex idx) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
virtual void
setVecPredRegFlat(RegIndex idx,
const ArmISA::VecPredRegContainer &val) override
const ArmISA::VecPredRegContainer &val)
{
panic("%s not implemented.", __FUNCTION__);
}
RegVal readCCRegFlat(RegIndex idx) const override;
void setCCRegFlat(RegIndex idx, RegVal val) override;
virtual RegVal readCCRegFlat(RegIndex idx) const;
virtual void setCCRegFlat(RegIndex idx, RegVal val);
/** @} */
// hardware transactional memory