From a10c57375595b9e0bfd6458d25fa362db7559c13 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 30 Aug 2020 02:40:21 -0700 Subject: [PATCH] arch,cpu: Get rid of the IsMemRef StaticInst flag. A comment at the top of StaticInstFlags.py says that if IsMemRef is set, exactly one of IsStore or IsLoad will be set. That's not strictly true since IsAtomic may be set as well, in which case neither IsStore or IsLoad will be set (in one example I found). The isMemRef accessor still exists, and now just ors the IsStore, IsLoad, and IsAtomic flags. Change-Id: Ic5ff104da68978273977a6eff2abab5dd0ae7fda Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33744 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/insts/tme64.cc | 3 --- src/arch/arm/isa/insts/data64.isa | 10 +++++----- src/arch/arm/isa/insts/macromem.isa | 4 ++-- src/arch/arm/isa/insts/misc.isa | 8 ++++---- src/arch/arm/isa/insts/neon64_mem.isa | 4 ++-- src/arch/arm/isa/insts/sve_mem.isa | 22 +++++++++++----------- src/arch/arm/isa/operands.isa | 2 +- src/arch/mips/isa/operands.isa | 2 +- src/arch/power/isa/operands.isa | 2 +- src/arch/riscv/isa/formats/amo.isa | 1 - src/arch/riscv/isa/operands.isa | 2 +- src/arch/sparc/isa/operands.isa | 2 +- src/arch/x86/isa/formats/monitor_mwait.isa | 1 - src/arch/x86/isa/operands.isa | 2 +- src/cpu/StaticInstFlags.py | 2 -- src/cpu/static_inst.hh | 6 +++++- 16 files changed, 35 insertions(+), 38 deletions(-) diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc index f7096d0b27..3629d34aeb 100644 --- a/src/arch/arm/insts/tme64.cc +++ b/src/arch/arm/insts/tme64.cc @@ -128,7 +128,6 @@ Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest) flags[IsHtmStart] = true; flags[IsInteger] = true; flags[IsLoad] = true; - flags[IsMemRef] = true; flags[IsMicroop] = true; flags[IsNonSpeculative] = true; } @@ -169,7 +168,6 @@ Tcancel64::Tcancel64(ExtMachInst machInst, uint64_t _imm) _numIntDestRegs = 0; _numCCDestRegs = 0; flags[IsLoad] = true; - flags[IsMemRef] = true; flags[IsMicroop] = true; flags[IsNonSpeculative] = true; flags[IsHtmCancel] = true; @@ -212,7 +210,6 @@ MicroTcommit64::MicroTcommit64(ExtMachInst machInst) _numCCDestRegs = 0; flags[IsHtmStop] = true; flags[IsLoad] = true; - flags[IsMemRef] = true; flags[IsMicroop] = true; flags[IsNonSpeculative] = true; } diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index d5a5869fbf..fb8968860a 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -392,7 +392,7 @@ let {{ "use_uops" : 0, "op_wb" : ";", "fa_code" : ";"}, - ['IsStore', 'IsMemRef']); + ['IsStore']); header_output += DCStore64Declare.subst(msrDCZVAIop); decoder_output += DCStore64Constructor.subst(msrDCZVAIop); exec_output += DCStore64Execute.subst(msrDCZVAIop); @@ -423,7 +423,7 @@ let {{ "use_uops" : 0, "op_wb" : ";", "fa_code" : cachem_fa}, - ['IsStore', 'IsMemRef']); + ['IsStore']); header_output += DCStore64Declare.subst(msrDCCVAUIop); decoder_output += DCStore64Constructor.subst(msrDCCVAUIop); exec_output += DCStore64Execute.subst(msrDCCVAUIop); @@ -447,7 +447,7 @@ let {{ "use_uops" : 0, "op_wb" : ";", "fa_code" : cachem_fa}, - ['IsStore', 'IsMemRef']); + ['IsStore']); header_output += DCStore64Declare.subst(msrDCCVACIop); decoder_output += DCStore64Constructor.subst(msrDCCVACIop); exec_output += DCStore64Execute.subst(msrDCCVACIop); @@ -472,7 +472,7 @@ let {{ "use_uops" : 0, "op_wb" : ";", "fa_code" : cachem_fa}, - ['IsStore', 'IsMemRef']); + ['IsStore']); header_output += DCStore64Declare.subst(msrDCCIVACIop); decoder_output += DCStore64Constructor.subst(msrDCCIVACIop); exec_output += DCStore64Execute.subst(msrDCCIVACIop); @@ -503,7 +503,7 @@ let {{ "use_uops" : 0, "op_wb" : ";", "fa_code" : cachem_fa}, - ['IsStore', 'IsMemRef']); + ['IsStore']); header_output += DCStore64Declare.subst(msrDCIVACIop); decoder_output += DCStore64Constructor.subst(msrDCIVACIop); exec_output += DCStore64Execute.subst(msrDCIVACIop); diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 1b9cdf7e8d..ad0f6778f3 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -252,7 +252,7 @@ let {{ 'memacc_code' : loadMemAccCode, 'ea_code' : simdEnabledCheckCode + eaCode, 'predicate_test' : predicateTest }, - [ 'IsMicroop', 'IsMemRef', 'IsLoad' ]) + [ 'IsMicroop', 'IsLoad' ]) storeIop = InstObjParams('strneon%(size)d_uop' % subst, 'MicroStrNeon%(size)dUop' % subst, 'MicroNeonMemOp', @@ -261,7 +261,7 @@ let {{ 'memacc_code' : storeMemAccCode, 'ea_code' : simdEnabledCheckCode + eaCode, 'predicate_test' : predicateTest }, - [ 'IsMicroop', 'IsMemRef', 'IsStore' ]) + [ 'IsMicroop', 'IsStore' ]) exec_output += NeonLoadExecute.subst(loadIop) + \ NeonLoadInitiateAcc.subst(loadIop) + \ diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index b2543b3da3..17c30ff698 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1149,7 +1149,7 @@ let {{ "postacc_code": "", "ea_code": McrDcimvacCode, "predicate_test": predicateTest}, - ['IsMemRef', 'IsStore']) + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop) exec_output += Mcr15Execute.subst(McrDcimvacIop) + \ @@ -1167,7 +1167,7 @@ let {{ "postacc_code": "", "ea_code": McrDccmvacCode, "predicate_test": predicateTest}, - ['IsMemRef', 'IsStore']) + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop) exec_output += Mcr15Execute.subst(McrDccmvacIop) + \ @@ -1185,7 +1185,7 @@ let {{ "postacc_code": "", "ea_code": McrDccmvauCode, "predicate_test": predicateTest}, - ['IsMemRef', 'IsStore']) + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop) exec_output += Mcr15Execute.subst(McrDccmvauIop) + \ @@ -1204,7 +1204,7 @@ let {{ "postacc_code": "", "ea_code": McrDccimvacCode, "predicate_test": predicateTest}, - ['IsMemRef', 'IsStore']) + ['IsStore']) header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop) decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop) exec_output += Mcr15Execute.subst(McrDccimvacIop) + \ diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa index e511f61d38..80741fb940 100644 --- a/src/arch/arm/isa/insts/neon64_mem.isa +++ b/src/arch/arm/isa/insts/neon64_mem.isa @@ -146,7 +146,7 @@ let {{ 'memacc_code' : loadMemAccCode, 'ea_code' : simd64EnabledCheckCode + eaCode, }, - [ 'IsMicroop', 'IsMemRef', 'IsLoad' ]) + [ 'IsMicroop', 'IsLoad' ]) loadIop.snippets["memacc_code"] += zeroSveVecRegUpperPartCode % \ "AA64FpDest" storeIop = InstObjParams(name + 'st', @@ -156,7 +156,7 @@ let {{ 'memacc_code' : storeMemAccCode, 'ea_code' : simd64EnabledCheckCode + eaCode, }, - [ 'IsMicroop', 'IsMemRef', 'IsStore' ]) + [ 'IsMicroop', 'IsStore' ]) exec_output += NeonLoadExecute64.subst(loadIop) + \ NeonLoadInitiateAcc64.subst(loadIop) + \ diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa index 66bfabb26c..8599900f4f 100644 --- a/src/arch/arm/isa/insts/sve_mem.isa +++ b/src/arch/arm/isa/insts/sve_mem.isa @@ -823,7 +823,7 @@ let {{ 'rden_code' : loadRdEnableCode, 'fault_code' : '', 'fa_code' : ''}, - ['IsMemRef', 'IsLoad']) + ['IsLoad']) storeIop = InstObjParams('str', 'SveStrPred' if isPred else 'SveStrVec', 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', @@ -833,7 +833,7 @@ let {{ 'memacc_code': storeMemAccCode, 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, - ['IsMemRef', 'IsStore']) + ['IsStore']) header_output += SveMemFillSpillOpDeclare.subst(loadIop) header_output += SveMemFillSpillOpDeclare.subst(storeIop) exec_output += ( @@ -1007,7 +1007,7 @@ let {{ 'ea_code' : sveEnabledCheckCode + eaCode, 'fault_code' : '', 'fa_code' : ''}, - ['IsMemRef', 'IsLoad']) + ['IsLoad']) storeIop = InstObjParams('st1', 'SveContigStoreSI' if offsetIsImm else 'SveContigStoreSS', 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', @@ -1017,7 +1017,7 @@ let {{ 'memacc_code': storeMemAccCode, 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, - ['IsMemRef', 'IsStore']) + ['IsStore']) faultIop = InstObjParams('ldff1' if firstFaulting else 'ldnf1', 'SveContigFFLoadSS' if firstFaulting else 'SveContigNFLoadSI', 'SveContigMemSS' if firstFaulting else 'SveContigMemSI', @@ -1028,7 +1028,7 @@ let {{ 'ea_code' : sveEnabledCheckCode + eaCode, 'fault_code' : faultCode, 'fa_code' : ''}, - ['IsMemRef', 'IsLoad']) + ['IsLoad']) faultIop.snippets['memacc_code'] = (ffrReadBackCode + faultIop.snippets['memacc_code']) if offsetIsImm: @@ -1091,7 +1091,7 @@ let {{ 'memacc_code': memAccCode, 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, - ['IsMemRef', 'IsLoad']) + ['IsLoad']) header_output += SveContigMemSIOpDeclare.subst(iop) exec_output += ( SveLoadAndReplExecute.subst(iop) + @@ -1158,7 +1158,7 @@ let {{ 'fault_status_reset_code' : faultStatusResetCode, 'pred_check_code' : predCheckCode, 'fa_code' : ''}, - ['IsMicroop', 'IsMemRef', 'IsLoad']) + ['IsMicroop', 'IsLoad']) storeIop = InstObjParams('st1', ('SveScatterStoreVIMicroop' if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM @@ -1170,7 +1170,7 @@ let {{ 'ea_code' : sveEnabledCheckCode + eaCode_store, 'pred_check_code' : predCheckCode, 'fa_code' : ''}, - ['IsMicroop', 'IsMemRef', 'IsStore']) + ['IsMicroop', 'IsStore']) if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM: header_output += SveIndexedMemVIMicroopDeclare.subst(loadIop) header_output += SveIndexedMemVIMicroopDeclare.subst(storeIop) @@ -1445,7 +1445,7 @@ let {{ 'memacc_code': loadMemAccCode, 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, - ['IsMemRef', 'IsLoad', 'IsMicroop']) + ['IsLoad', 'IsMicroop']) storeIop = InstObjParams('stxx', 'SveStoreRegImmMicroop' if offsetIsImm else 'SveStoreRegRegMicroop', @@ -1455,7 +1455,7 @@ let {{ 'memacc_code': storeMemAccCode, 'ea_code' : sveEnabledCheckCode + eaCode, 'fa_code' : ''}, - ['IsMemRef', 'IsStore', 'IsMicroop']) + ['IsStore', 'IsMicroop']) if offsetIsImm: header_output += SveStructMemSIMicroopDeclare.subst(loadIop) header_output += SveStructMemSIMicroopDeclare.subst(storeIop) @@ -1528,7 +1528,7 @@ let {{ 'ea_code': sveEnabledCheckCode + eaCode, 'fault_code': '', 'fa_code': ''}, - ['IsMemRef', 'IsLoad']) + ['IsLoad']) if offsetIsImm: header_output += SveContigMemSIOpDeclare.subst(iop) else: diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index e9ee098e6b..134c51f80b 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -681,7 +681,7 @@ def operands {{ 'XURc' : intRegX64('urc'), #Memory Operand - 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), + 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), srtNormal), #PCState fields 'RawPC': pcStateReg('pc', srtPC), diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 26c5a543fe..3cb2d431a3 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -144,7 +144,7 @@ def operands {{ 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1), #Memory Operand - 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 4), #Program Counter Operands 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4), diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 397364f438..e77fde2966 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -54,7 +54,7 @@ def operands {{ 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5), # Memory Operand - 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), + 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8), # Program counter and next 'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9), diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index 7b151bd9cf..7d01145e3c 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -207,7 +207,6 @@ def template AtomicMemOpRMWConstructor {{ %(constructor)s; // overwrite default flags - flags[IsMemRef] = true; flags[IsLoad] = false; flags[IsStore] = false; flags[IsAtomic] = true; diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa index 12f55778cc..78cd5f9e19 100644 --- a/src/arch/riscv/isa/operands.isa +++ b/src/arch/riscv/isa/operands.isa @@ -72,7 +72,7 @@ def operands {{ 'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2), #Memory Operand - 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5), + 'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 5), #Program Counter Operands 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7), diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 2c1eec6b19..7a2da13728 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -187,6 +187,6 @@ def operands {{ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), # Mem gets a large number so it's always last - 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) + 'Mem': ('Mem', 'udw', None, (None, 'IsLoad', 'IsStore'), 100) }}; diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa index 809623de02..b5fe34c51d 100644 --- a/src/arch/x86/isa/formats/monitor_mwait.isa +++ b/src/arch/x86/isa/formats/monitor_mwait.isa @@ -90,7 +90,6 @@ output header {{ OpClass __opClass) : X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass) { - flags[IsMemRef] = 1; flags[IsLoad] = 1; } diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 64c83c65cc..504deb73fe 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -207,5 +207,5 @@ def operands {{ 'TscOp': controlReg('MISCREG_TSC', 212), 'M5Reg': squashCReg('MISCREG_M5_REG', 213), 'Mem': ('Mem', 'uqw', None, \ - ('IsMemRef', 'IsLoad', 'IsStore'), 300) + (None, 'IsLoad', 'IsStore'), 300) }}; diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py index e11ee6813a..4775289407 100644 --- a/src/cpu/StaticInstFlags.py +++ b/src/cpu/StaticInstFlags.py @@ -36,7 +36,6 @@ from m5.params import * # one of these two flags set, it is possible for an instruction to have # neither (e.g., direct unconditional branches, memory barriers) or both # (e.g., an FP/int conversion). -# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set. # - If IsControl is set, then exactly one of IsDirectControl or IsIndirect # Control will be set, and exactly one of IsCondControl or IsUncondControl # will be set. @@ -54,7 +53,6 @@ class StaticInstFlags(Enum): 'IsVector', # References Vector regs. 'IsVectorElem', # References Vector reg elems. - 'IsMemRef', # References memory (load, store, or prefetch) 'IsLoad', # Reads from memory (load or prefetch). 'IsStore', # Writes to memory. 'IsAtomic', # Does atomic RMW to memory. diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 258749c4c8..65561706de 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -157,7 +157,11 @@ class StaticInst : public RefCounted, public StaticInstFlags bool isNop() const { return flags[IsNop]; } - bool isMemRef() const { return flags[IsMemRef]; } + bool + isMemRef() const + { + return flags[IsLoad] || flags[IsStore] || flags[IsAtomic]; + } bool isLoad() const { return flags[IsLoad]; } bool isStore() const { return flags[IsStore]; } bool isAtomic() const { return flags[IsAtomic]; }