diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py
index 586e77caed..5e82fd9f9f 100644
--- a/src/cpu/trace/TraceCPU.py
+++ b/src/cpu/trace/TraceCPU.py
@@ -55,10 +55,6 @@ class TraceCPU(ClockedObject):
     def require_caches(cls):
         return True
 
-    @classmethod
-    def support_take_over(cls):
-        return True
-
     system = Param.System(Parent.any, "system object")
 
     icache_port = RequestPort("Instruction Port")
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index ab14c8784a..d5c6b4fb3c 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -39,6 +39,7 @@
 
 #include "base/compiler.hh"
 #include "sim/sim_exit.hh"
+#include "sim/system.hh"
 
 namespace gem5
 {
@@ -94,14 +95,6 @@ TraceCPU::updateNumOps(uint64_t rob_num)
     }
 }
 
-void
-TraceCPU::takeOverFrom(BaseCPU *oldCPU)
-{
-    // Unbind the ports of the old CPU and bind the ports of the TraceCPU.
-    getInstPort().takeOverFrom(&oldCPU->getInstPort());
-    getDataPort().takeOverFrom(&oldCPU->getDataPort());
-}
-
 void
 TraceCPU::init()
 {
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index f3f5c38786..d54b3c4227 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -45,10 +45,10 @@
 #include <unordered_map>
 
 #include "base/statistics.hh"
-#include "cpu/base.hh"
 #include "debug/TraceCPUData.hh"
 #include "debug/TraceCPUInst.hh"
 #include "mem/packet.hh"
+#include "mem/port.hh"
 #include "mem/request.hh"
 #include "params/TraceCPU.hh"
 #include "proto/inst_dep_record.pb.h"
@@ -163,14 +163,6 @@ class TraceCPU : public ClockedObject
      */
     void updateNumOps(uint64_t rob_num);
 
-    /*
-     * When resuming from checkpoint in FS mode, the TraceCPU takes over from
-     * the old cpu. This function overrides the takeOverFrom() function in the
-     * BaseCPU. It unbinds the ports of the old CPU and binds the ports of the
-     * TraceCPU.
-     */
-    void takeOverFrom(BaseCPU *oldCPU);
-
     /**
      * When instruction cache port receives a retry, schedule event
      * icacheNextEvent.