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cpu: Stop using NumVecElemPerVecReg.

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Use the register classes regName method, or if necessary, the ratio
between the size of the vector register file and the vector element
register file.

Change-Id: Ibf63ce2b3cc3e3cc3261e5a9b8dcbfdc0af5035b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49164
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-08-10 00:16:54 -07:00
parent 0eba590d01
commit a00a6f953f
5 changed files with 30 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/minor/dyn_inst.cc
View File

@@ -152,8 +152,7 @@ printRegName(std::ostream &os, const RegId& reg,
os << 'v' << reg.index();
break;
case VecElemClass:
os << 'v' << (reg.index() / TheISA::NumVecElemPerVecReg) << '[' <<
(reg.index() % TheISA::NumVecElemPerVecReg) << ']';
os << reg_class.regName(reg);
break;
case IntRegClass:
if (reg.index() == reg_class.zeroReg()) {

5
src/cpu/o3/inst_queue.cc
View File

@@ -99,11 +99,14 @@ InstructionQueue::InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
{
assert(fuPool);
const auto &reg_classes = params.isa[0]->regClasses();
// Set the number of total physical registers
// As the vector registers have two addressing modes, they are added twice
numPhysRegs = params.numPhysIntRegs + params.numPhysFloatRegs +
params.numPhysVecRegs +
params.numPhysVecRegs * TheISA::NumVecElemPerVecReg +
params.numPhysVecRegs * (
reg_classes.at(VecElemClass).size() /
reg_classes.at(VecRegClass).size()) +
params.numPhysVecPredRegs +
params.numPhysCCRegs;

24
src/cpu/o3/regfile.cc
View File

@@ -54,26 +54,30 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalVecRegs,
unsigned _numPhysicalVecPredRegs,
unsigned _numPhysicalCCRegs,
const BaseISA::RegClasses &regClasses)
const BaseISA::RegClasses &classes)
: intRegFile(_numPhysicalIntRegs),
floatRegFile(_numPhysicalFloatRegs),
vectorRegFile(_numPhysicalVecRegs),
vectorElemRegFile(_numPhysicalVecRegs * TheISA::NumVecElemPerVecReg),
vectorElemRegFile(_numPhysicalVecRegs * (
classes.at(VecElemClass).size() /
classes.at(VecRegClass).size())),
vecPredRegFile(_numPhysicalVecPredRegs),
ccRegFile(_numPhysicalCCRegs),
numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs),
numPhysicalVecRegs(_numPhysicalVecRegs),
numPhysicalVecElemRegs(_numPhysicalVecRegs *
TheISA::NumVecElemPerVecReg),
numPhysicalVecElemRegs(_numPhysicalVecRegs * (
classes.at(VecElemClass).size() /
classes.at(VecRegClass).size())),
numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
numPhysicalCCRegs(_numPhysicalCCRegs),
totalNumRegs(_numPhysicalIntRegs
+ _numPhysicalFloatRegs
+ _numPhysicalVecRegs
+ _numPhysicalVecRegs * TheISA::NumVecElemPerVecReg
+ numPhysicalVecElemRegs
+ _numPhysicalVecPredRegs
+ _numPhysicalCCRegs)
+ _numPhysicalCCRegs),
regClasses(classes)
{
RegIndex phys_reg;
RegIndex flat_reg_idx = 0;
@@ -99,9 +103,7 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
}
// The next batch of the registers are the vector element physical
// registers; put them onto the vector free list.
for (phys_reg = 0;
phys_reg < numPhysicalVecRegs * TheISA::NumVecElemPerVecReg;
phys_reg++) {
for (phys_reg = 0; phys_reg < numPhysicalVecElemRegs; phys_reg++) {
vecElemIds.emplace_back(VecElemClass, phys_reg, flat_reg_idx++);
}
@@ -150,9 +152,7 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
assert(vecRegIds[reg_idx].index() == reg_idx);
}
freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
for (reg_idx = 0;
reg_idx < numPhysicalVecRegs * TheISA::NumVecElemPerVecReg;
reg_idx++) {
for (reg_idx = 0; reg_idx < numPhysicalVecElemRegs; reg_idx++) {
assert(vecElemIds[reg_idx].index() == reg_idx);
}
freeList->addRegs(vecElemIds.begin(), vecElemIds.end());

16
src/cpu/o3/regfile.hh
View File

@@ -132,6 +132,8 @@ class PhysRegFile
/** Total number of physical registers. */
unsigned totalNumRegs;
const BaseISA::RegClasses &regClasses;
public:
/**
* Constructs a physical register file with the specified amount of
@@ -142,7 +144,7 @@ class PhysRegFile
unsigned _numPhysicalVecRegs,
unsigned _numPhysicalVecPredRegs,
unsigned _numPhysicalCCRegs,
const BaseISA::RegClasses &regClasses);
const BaseISA::RegClasses &classes);
/**
* Destructor to free resources
@@ -227,10 +229,8 @@ class PhysRegFile
{
assert(phys_reg->is(VecElemClass));
RegVal val = vectorElemRegFile[phys_reg->index()];
DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
" has data %#x\n",
phys_reg->index() / TheISA::NumVecElemPerVecReg,
phys_reg->index() % TheISA::NumVecElemPerVecReg, val);
DPRINTF(IEW, "RegFile: Access to vector register element %d,"
" has data %#x\n", phys_reg->index(), val);
return val;
}
@@ -311,10 +311,8 @@ class PhysRegFile
{
assert(phys_reg->is(VecElemClass));
DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
" %#x\n",
phys_reg->index() / TheISA::NumVecElemPerVecReg,
phys_reg->index() % TheISA::NumVecElemPerVecReg, val);
DPRINTF(IEW, "RegFile: Setting vector register element %d to %#x\n",
phys_reg->index(), val);
vectorElemRegFile[phys_reg->index()] = val;
}

12
src/cpu/simple_thread.hh
View File

@@ -313,9 +313,9 @@ class SimpleThread : public ThreadState, public ThreadContext
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < vecElemRegs.size());
RegVal regVal = readVecElemFlat(flatIndex);
DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
" %#x.\n", reg.index() % TheISA::NumVecElemPerVecReg,
reg.index() / TheISA::NumVecElemPerVecReg, flatIndex, regVal);
DPRINTF(VecRegs, "Reading vector register element %s (%d) as %#x.\n",
isa->regClasses().at(VecElemClass).regName(reg), flatIndex,
regVal);
return regVal;
}
@@ -395,9 +395,9 @@ class SimpleThread : public ThreadState, public ThreadContext
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < vecElemRegs.size());
setVecElemFlat(flatIndex, val);
DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
" %#x.\n", reg.index() % TheISA::NumVecElemPerVecReg,
reg.index() / TheISA::NumVecElemPerVecReg, flatIndex, val);
DPRINTF(VecRegs, "Setting vector register element %s (%d) to %#x.\n",
isa->regClasses().at(VecElemClass).regName(reg), flatIndex,
val);
}
void