From 9fb5ce5cd3a425dffcde18caed36f428afdf3cbd Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Tue, 21 Feb 2023 11:45:44 +0800
Subject: [PATCH] arch-riscv,dev: Fix behavior issues of PLIC

1. Fix reserved size between enable memory map and threshold memory
map. The number of enablePadding should be the number of context in
PLIC
2. writePriority to memory should update

Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68198
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
---
 src/dev/riscv/plic.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index b8f765a17c..371af9e78a 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -203,7 +203,7 @@ Plic::PlicRegisters::init()
         - plic->nSrc32 * 4;
     reserved.emplace_back("reserved1", reserve1_size);
     const size_t reserve2_size = thresholdStart - enableStart
-        - plic->nSrc32 * plic->nContext * enablePadding;
+        - plic->nContext * enablePadding;
     reserved.emplace_back("reserved2", reserve2_size);
     const size_t reserve3_size = plic->pioSize - thresholdStart
         - plic->nContext * thresholdPadding;
@@ -333,6 +333,8 @@ void
 Plic::writeThreshold(Register32& reg, const uint32_t& data,
     const int context_id)
 {
+    reg.update(data);
+
     DPRINTF(Plic,
         "Threshold updated - context: %d, val: %d\n",
         context_id, reg.get());