CPU: Round-two unifying instr/data CPU ports across models

This patch continues the unification of how the different CPU models
create and share their instruction and data ports. Most importantly,
it forces every CPU to have an instruction and a data port, and gives
these ports explicit getters in the BaseCPU (getDataPort and
getInstPort). The patch helps in simplifying the code, make
assumptions more explicit, andfurther ease future patches related to
the CPU ports.

The biggest changes are in the in-order model (that was not modified
in the previous unification patch), which now moves the ports from the
CacheUnit to the CPU. It also distinguishes the instruction fetch and
load-store unit from the rest of the resources, and avoids the use of
indices and casting in favour of keeping track of these two units
explicitly (since they are always there anyways). The atomic, timing
and O3 model simply return references to their already existing ports.

src/cpu/simple/atomic.cc

@@ -68,16 +68,12 @@ AtomicSimpleCPU::TickEvent::description() const
 Port *
 AtomicSimpleCPU::getPort(const string &if_name, int idx)
 {
-    if (if_name == "dcache_port")
-        return &dcachePort;
-    else if (if_name == "icache_port")
-        return &icachePort;
-    else if (if_name == "physmem_port") {
+    if (if_name == "physmem_port") {
         hasPhysMemPort = true;
         return &physmemPort;
+    } else {
+        return BaseCPU::getPort(if_name, idx);
     }
-    else
-        panic("No Such Port\n");
 }
 
 void

src/cpu/simple/atomic.hh

@@ -101,8 +101,20 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     Range<Addr> physMemAddr;
 
+  protected:
+
+    /** Return a reference to the data port. */
+    virtual CpuPort &getDataPort() { return dcachePort; }
+
+    /** Return a reference to the instruction port. */
+    virtual CpuPort &getInstPort() { return icachePort; }
+
   public:
 
+    /**
+     * Override the getPort of the BaseCPU so that we can provide a pointer
+     * to the physmemPort, unique to the Atomic CPU.
+     */
     virtual Port *getPort(const std::string &if_name, int idx = -1);
 
     virtual void serialize(std::ostream &os);

src/cpu/simple/base.hh

@@ -67,7 +67,6 @@
 
 // forward declarations
 class Checkpoint;
-class MemObject;
 class Process;
 class Processor;
 class ThreadContext;

src/cpu/simple/timing.cc

@@ -60,17 +60,6 @@
 using namespace std;
 using namespace TheISA;
 
-Port *
-TimingSimpleCPU::getPort(const std::string &if_name, int idx)
-{
-    if (if_name == "dcache_port")
-        return &dcachePort;
-    else if (if_name == "icache_port")
-        return &icachePort;
-    else
-        panic("No Such Port\n");
-}
-
 void
 TimingSimpleCPU::init()
 {

src/cpu/simple/timing.hh

@@ -231,9 +231,15 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     Tick previousTick;
 
-  public:
+  protected:
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+     /** Return a reference to the data port. */
+    virtual CpuPort &getDataPort() { return dcachePort; }
+
+    /** Return a reference to the instruction port. */
+    virtual CpuPort &getInstPort() { return icachePort; }
+
+  public:
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);