diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ffd9cfc6b8..f55235da11 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1879,6 +1879,18 @@ ISA::unserialize(CheckpointIn &cp) { DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS); + + for (auto idx = 0; idx < NUM_MISCREGS; idx++) { + if (!lookUpMiscReg[idx].info[MISCREG_UNSERIALIZE] && + miscRegs[idx] != lookUpMiscReg[idx].reset()) { + warn("Checkpoint value for register %s does not match " + "current configuration (checkpointed: %#x, current: %#x)", + miscRegName[idx], miscRegs[idx], + lookUpMiscReg[idx].reset()); + miscRegs[idx] = lookUpMiscReg[idx].reset(); + } + } + CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); } diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 265a697781..3a32623292 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1125,6 +1125,7 @@ namespace ArmISA MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a // arch generic counter) + MISCREG_UNSERIALIZE, // Should the checkpointed value be restored? MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it // tells whether the instruction should raise a // warning or fail @@ -1277,6 +1278,12 @@ namespace ArmISA return *this; } chain + unserialize(bool v = true) const + { + entry.info[MISCREG_UNSERIALIZE] = v; + return *this; + } + chain warnNotFail(bool v = true) const { entry.info[MISCREG_WARN_NOT_FAIL] = v; @@ -1595,7 +1602,7 @@ namespace ArmISA : entry(e) { // force unimplemented registers to be thusly declared - implemented(1); + implemented(1).unserialize(1); } };