From 9d9b7848bb6f39efb88f6d8efc96baf4c3452e3e Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 2 Feb 2024 10:39:25 +0000 Subject: [PATCH] arch-arm: Properly compute EL even in stage2 walks This is done in order to differentiate between EL0 (unprivileged) and EL1. Effectively it won't change much as most of the decisions are now taken according to the translation regime which will be the same regardless (EL10) Change-Id: I218037e9c19cf638aff05c51869e439204d9af69 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-by: Andreas Sandberg --- src/arch/arm/table_walker.cc | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 077abe653e..8530c95414 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -332,18 +332,15 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, currState->startTime = curTick(); currState->tc = _tc; - // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 - // aarch32/translation/translation/AArch32.TranslateAddress dictates - // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. + currState->el = + MMU::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), + _tc->readMiscReg(MISCREG_SCR_EL3), + tranType); + if (isStage2) { - currState->el = EL1; currState->regime = TranslationRegime::EL10; currState->aarch64 = ELIs64(_tc, EL2); } else { - currState->el = - MMU::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), - _tc->readMiscReg(MISCREG_SCR_EL3), - tranType); currState->regime = translationRegime(_tc, currState->el); currState->aarch64 =