diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index a343658bea..620302ff8e 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -348,7 +348,6 @@ class ThreadContext : public gem5::ThreadContext
     }
 
     void pcStateNoRecord(const PCStateBase &val) override { pcState(val); }
-    MicroPC microPC() const override { return 0; }
 
     const PCStateBase &pcState() const override;
     void pcState(const PCStateBase &val) override;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3d29d05eb7..37b19aa235 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -367,7 +367,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
         thread->pcState(val);
     }
     Addr instAddr() { return thread->instAddr(); }
-    MicroPC microPC() { return thread->microPC(); }
     //////////////////////////////////////////
 
     RegVal
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index dfc952472a..81c497318b 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -343,9 +343,6 @@ class CheckerThreadContext : public ThreadContext
     /** Reads this thread's PC. */
     Addr instAddr() const override { return actualTC->instAddr(); }
 
-    /** Reads this thread's next PC. */
-    MicroPC microPC() const override { return actualTC->microPC(); }
-
     RegVal
     readMiscRegNoEffect(RegIndex misc_reg) const override
     {
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ed462e059a..4a3b3350cf 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -314,9 +314,6 @@ class Commit
     /** Returns the PC of a specific thread. */
     Addr instAddr(ThreadID tid) { return pc[tid]->instAddr(); }
 
-    /** Reads the micro PC of a specific thread. */
-    Addr microPC(ThreadID tid) { return pc[tid]->microPC(); }
-
   private:
     /** Time buffer interface. */
     TimeBuffer<TimeStruct> *timeBuffer;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 462c0291ec..6e88a28d27 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1325,12 +1325,6 @@ CPU::instAddr(ThreadID tid)
     return commit.instAddr(tid);
 }
 
-MicroPC
-CPU::microPC(ThreadID tid)
-{
-    return commit.microPC(tid);
-}
-
 void
 CPU::squashFromTC(ThreadID tid)
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e7dd06547a..46dbefc16a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -393,9 +393,6 @@ class CPU : public BaseCPU
     /** Reads the commit PC of a specific thread. */
     Addr instAddr(ThreadID tid);
 
-    /** Reads the commit micro PC of a specific thread. */
-    MicroPC microPC(ThreadID tid);
-
     /** Initiates a squash of all in-flight instructions for a given
      * thread.  The source of the squash is an external update of
      * state through the TC.
diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index 36591aed72..89a7594b79 100644
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -219,7 +219,7 @@ DynInst::~DynInst()
             DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
                      fetch,
                      instAddr(),
-                     microPC(),
+                     pcState().microPC(),
                      seqNum,
                      staticInst->disassemble(instAddr()));
 
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 832d5e889f..7ffb779c4f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -518,9 +518,6 @@ class DynInst : public ExecContext, public RefCounted
     /** Returns the predicted PC immediately after the branch. */
     Addr predInstAddr() { return predPC->instAddr(); }
 
-    /** Returns the predicted micro PC after the branch */
-    Addr predMicroPC() { return predPC->microPC(); }
-
     /** Returns whether the instruction was predicted taken or not. */
     bool readPredTaken() { return instFlags[PredTaken]; }
 
@@ -910,9 +907,6 @@ class DynInst : public ExecContext, public RefCounted
     /** Read the PC of this instruction. */
     Addr instAddr() const { return pc->instAddr(); }
 
-    /**Read the micro PC of this instruction. */
-    Addr microPC() const { return pc->microPC(); }
-
     bool readPredicate() const override { return instFlags[Predicate]; }
 
     void
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index c50371efac..ea3ed742ea 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -295,13 +295,6 @@ class ThreadContext : public gem5::ThreadContext
         return cpu->instAddr(thread->threadId());
     }
 
-    /** Reads this thread's next PC. */
-    MicroPC
-    microPC() const override
-    {
-        return cpu->microPC(thread->threadId());
-    }
-
     /** Reads a miscellaneous register. */
     RegVal
     readMiscRegNoEffect(RegIndex misc_reg) const override
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 3eb24fa5aa..aacd0dc033 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -92,7 +92,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     isCpuDrained() const
     {
         SimpleExecContext &t_info = *threadInfo[curThread];
-        return t_info.thread->microPC() == 0 &&
+        return t_info.thread->pcState().microPC() == 0 &&
             !locked && !t_info.stayAtPC;
     }
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9f1ce4a5e6..82e4cc8206 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -180,7 +180,7 @@ TimingSimpleCPU::switchOut()
     assert(!fetchEvent.scheduled());
     assert(_status == BaseSimpleCPU::Running || _status == Idle);
     assert(!t_info.stayAtPC);
-    assert(thread->microPC() == 0);
+    assert(thread->pcState().microPC() == 0);
 
     updateCycleCounts();
     updateCycleCounters(BaseCPU::CPU_STATE_ON);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 5a21c0eee7..b2cc4e7ffd 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -363,7 +363,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
         SimpleExecContext& t_info = *threadInfo[curThread];
         SimpleThread* thread = t_info.thread;
 
-        return thread->microPC() == 0 && !t_info.stayAtPC &&
+        return thread->pcState().microPC() == 0 && !t_info.stayAtPC &&
                !fetchEvent.scheduled();
     }
 
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 31e02f763f..ac13d15e51 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -430,7 +430,6 @@ class SimpleThread : public ThreadState, public ThreadContext
     }
 
     Addr instAddr() const override  { return _pcState->instAddr(); }
-    MicroPC microPC() const override { return _pcState->microPC(); }
     bool readPredicate() const { return predicate; }
     void setPredicate(bool val) { predicate = val; }
 
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 07eb7bbe15..979f70c594 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -237,8 +237,6 @@ class ThreadContext : public PCEventScope
 
     virtual Addr instAddr() const = 0;
 
-    virtual MicroPC microPC() const = 0;
-
     virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
 
     virtual RegVal readMiscReg(RegIndex misc_reg) = 0;