diff --git a/src/arch/SConscript b/src/arch/SConscript index 7fec19ec08..13ab8fbd75 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -69,7 +69,6 @@ env.SwitchingHeaders( stacktrace.hh types.hh utility.hh - vtophys.hh '''), env.subst('${TARGET_ISA}')) diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 409e287db6..e51437e49c 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -88,7 +88,6 @@ if env['TARGET_ISA'] == 'arm': Source('tlb.cc') Source('tlbi_op.cc') Source('utility.cc') - Source('vtophys.cc') SimObject('ArmFsWorkload.py') SimObject('ArmInterrupts.py') diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index 933742bc10..1d18d21512 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -45,7 +45,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" -#include "arch/arm/vtophys.hh" #include "sim/serialize.hh" namespace ArmISA { diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index 1c764f4f1f..b2977e5133 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -140,7 +140,7 @@ #include "arch/arm/registers.hh" #include "arch/arm/system.hh" #include "arch/arm/utility.hh" -#include "arch/arm/vtophys.hh" +#include "arch/generic/tlb.hh" #include "base/chunk_generator.hh" #include "base/intmath.hh" #include "base/remote_gdb.hh" @@ -166,6 +166,26 @@ using namespace std; using namespace ArmISA; +static bool +tryTranslate(ThreadContext *tc, Addr addr) +{ + // Set up a functional memory Request to pass to the TLB + // to get it to translate the vaddr to a paddr + auto req = std::make_shared(addr, 64, 0x40, -1, 0, 0); + + // Check the TLBs for a translation + // It's possible that there is a valid translation in the tlb + // that is no loger valid in the page table in memory + // so we need to check here first + // + // Calling translateFunctional invokes a table-walk if required + // so we should always succeed + auto *dtb = tc->getDTBPtr(); + auto *itb = tc->getITBPtr(); + return dtb->translateFunctional(req, tc, BaseTLB::Read) == NoFault || + itb->translateFunctional(req, tc, BaseTLB::Read) == NoFault; +} + RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port) : BaseRemoteGDB(_system, tc, _port), regCache32(this), regCache64(this) { @@ -179,7 +199,7 @@ RemoteGDB::acc(Addr va, size_t len) { if (FullSystem) { for (ChunkGenerator gen(va, len, PageBytes); !gen.done(); gen.next()) { - if (!virtvalid(context(), gen.addr())) { + if (!tryTranslate(context(), gen.addr())) { DPRINTF(GDBAcc, "acc: %#x mapping is invalid\n", va); return false; } diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc index 5decb145dc..4604524277 100644 --- a/src/arch/arm/stacktrace.cc +++ b/src/arch/arm/stacktrace.cc @@ -31,7 +31,6 @@ #include #include "arch/arm/isa_traits.hh" -#include "arch/arm/vtophys.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 4efbe02869..767222a24c 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -46,7 +46,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/pagetable.hh" #include "arch/arm/utility.hh" -#include "arch/arm/vtophys.hh" #include "arch/generic/tlb.hh" #include "base/statistics.hh" #include "mem/request.hh" diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 72b03be992..393f141b03 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -43,7 +43,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/system.hh" #include "arch/arm/tlb.hh" -#include "arch/arm/vtophys.hh" #include "cpu/base.hh" #include "cpu/checker/cpu.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc deleted file mode 100644 index 62f4d78f4c..0000000000 --- a/src/arch/arm/vtophys.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2010, 2012-2013 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/arm/vtophys.hh" - -#include - -#include "arch/arm/faults.hh" -#include "arch/arm/table_walker.hh" -#include "arch/arm/tlb.hh" -#include "base/chunk_generator.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" - -using namespace std; -using namespace ArmISA; - -static std::pair -try_translate(ThreadContext *tc, Addr addr) -{ - Fault fault; - // Set up a functional memory Request to pass to the TLB - // to get it to translate the vaddr to a paddr - auto req = std::make_shared(addr, 64, 0x40, -1, 0, 0); - BaseTLB *tlb; - - // Check the TLBs for a translation - // It's possible that there is a valid translation in the tlb - // that is no loger valid in the page table in memory - // so we need to check here first - // - // Calling translateFunctional invokes a table-walk if required - // so we should always succeed - tlb = tc->getDTBPtr(); - fault = tlb->translateFunctional(req, tc, BaseTLB::Read); - if (fault == NoFault) - return std::make_pair(true, req->getPaddr()); - - tlb = tc->getITBPtr(); - fault = tlb->translateFunctional(req, tc, BaseTLB::Read); - if (fault == NoFault) - return std::make_pair(true, req->getPaddr()); - - return std::make_pair(false, 0); -} - -Addr -ArmISA::vtophys(ThreadContext *tc, Addr addr) -{ - const std::pair translation(try_translate(tc, addr)); - - if (translation.first) - return translation.second; - else - panic("Table walkers support functional accesses. " - "We should never get here."); -} - -bool -ArmISA::virtvalid(ThreadContext *tc, Addr vaddr) -{ - const std::pair translation(try_translate(tc, vaddr)); - - return translation.first; -} - - diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh deleted file mode 100644 index 7810b9885b..0000000000 --- a/src/arch/arm/vtophys.hh +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_ARM_VTOPHYS_HH__ -#define __ARCH_ARM_VTOPHYS_HH__ - -#include "arch/arm/isa_traits.hh" -#include "arch/arm/utility.hh" - -class ThreadContext; - -namespace ArmISA -{ - -inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } - -Addr vtophys(ThreadContext *tc, Addr vaddr); -bool virtvalid(ThreadContext *tc, Addr vaddr); - -} // namespace ArmISA - -#endif // __ARCH_ARM_VTOPHYS_HH__ - diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 0e697781ea..c426760eb2 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -46,7 +46,6 @@ if env['TARGET_ISA'] == 'mips': Source('system.cc') Source('tlb.cc') Source('utility.cc') - Source('vtophys.cc') SimObject('MipsInterrupts.py') SimObject('MipsISA.py') diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc index 8e305fa6f0..cff1cefcf8 100644 --- a/src/arch/mips/linux/system.cc +++ b/src/arch/mips/linux/system.cc @@ -40,7 +40,6 @@ #include "arch/generic/linux/threadinfo.hh" #include "arch/mips/idle_event.hh" #include "arch/mips/system.hh" -#include "arch/vtophys.hh" #include "base/loader/symtab.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc index 9dbe395bee..48138eec78 100644 --- a/src/arch/mips/remote_gdb.cc +++ b/src/arch/mips/remote_gdb.cc @@ -136,7 +136,6 @@ #include #include "arch/mips/decoder.hh" -#include "arch/mips/vtophys.hh" #include "cpu/thread_state.hh" #include "debug/GDBAcc.hh" #include "debug/GDBMisc.hh" diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc index c2fdb2362a..651719a02b 100644 --- a/src/arch/mips/stacktrace.cc +++ b/src/arch/mips/stacktrace.cc @@ -31,7 +31,6 @@ #include #include "arch/mips/isa_traits.hh" -#include "arch/mips/vtophys.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc index 028d570a31..bef77be331 100644 --- a/src/arch/mips/system.cc +++ b/src/arch/mips/system.cc @@ -30,7 +30,6 @@ #include "arch/mips/system.hh" #include "arch/mips/registers.hh" -#include "arch/mips/vtophys.hh" #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index bfe424d5cf..b17f9ec342 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -36,7 +36,6 @@ #include "arch/mips/isa_traits.hh" #include "arch/mips/pagetable.hh" #include "arch/mips/utility.hh" -#include "arch/mips/vtophys.hh" #include "base/statistics.hh" #include "mem/request.hh" #include "params/MipsTLB.hh" diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index d2c964847e..b42635fc44 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -32,7 +32,6 @@ #include "arch/mips/isa_traits.hh" #include "arch/mips/registers.hh" -#include "arch/mips/vtophys.hh" #include "base/bitfield.hh" #include "base/logging.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc deleted file mode 100644 index b4711fa339..0000000000 --- a/src/arch/mips/vtophys.cc +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/mips/vtophys.hh" - -#include "base/logging.hh" - -Addr -MipsISA::vtophys(ThreadContext *tc, Addr addr) -{ - fatal("VTOPHYS: Unimplemented on MIPS\n"); -} - diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh deleted file mode 100644 index 045d5baa76..0000000000 --- a/src/arch/mips/vtophys.hh +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_MIPS_VTOPHYS_HH__ -#define __ARCH_MIPS_VTOPHYS_HH__ - -#include "arch/mips/isa_traits.hh" -#include "arch/mips/utility.hh" - -class ThreadContext; - -namespace MipsISA -{ - -Addr vtophys(ThreadContext *tc, Addr vaddr); - -} // namespace MipsISA - -#endif // __ARCH_MIPS_VTOPHYS_HH__ - diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index b4878fd13a..93be38c4c8 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -49,7 +49,6 @@ if env['TARGET_ISA'] == 'power': Source('stacktrace.cc') Source('tlb.cc') Source('utility.cc') - Source('vtophys.cc') SimObject('PowerInterrupts.py') SimObject('PowerISA.py') diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh index 2e79da03e2..3aecf11244 100644 --- a/src/arch/power/pagetable.hh +++ b/src/arch/power/pagetable.hh @@ -34,9 +34,11 @@ #include "arch/power/isa_traits.hh" #include "arch/power/utility.hh" -#include "arch/power/vtophys.hh" -namespace PowerISA { +namespace PowerISA +{ + +static inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } struct VAddr { diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc index 8c27511688..ccee0b1327 100644 --- a/src/arch/power/remote_gdb.cc +++ b/src/arch/power/remote_gdb.cc @@ -136,7 +136,6 @@ #include -#include "arch/power/vtophys.hh" #include "cpu/thread_state.hh" #include "debug/GDBAcc.hh" #include "debug/GDBMisc.hh" diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index 044054cd36..23359ca9cb 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -38,7 +38,6 @@ #include "arch/power/isa_traits.hh" #include "arch/power/pagetable.hh" #include "arch/power/utility.hh" -#include "arch/power/vtophys.hh" #include "base/statistics.hh" #include "mem/request.hh" #include "params/PowerTLB.hh" diff --git a/src/arch/power/vtophys.cc b/src/arch/power/vtophys.cc deleted file mode 100644 index 973facc318..0000000000 --- a/src/arch/power/vtophys.cc +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2012 Google - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/power/vtophys.hh" - -using namespace std; - -Addr -PowerISA::vtophys(ThreadContext *tc, Addr addr) -{ - fatal("vtophys: Unimplemented on POWER\n"); -} - diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh deleted file mode 100644 index 650fb5f1f0..0000000000 --- a/src/arch/power/vtophys.hh +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * Copyright (c) 2009 The University of Edinburgh - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_POWER_VTOPHYS_HH__ -#define __ARCH_POWER_VTOPHYS_HH__ - -#include "arch/power/isa_traits.hh" -#include "arch/power/utility.hh" - -class ThreadContext; - -namespace PowerISA -{ - -Addr vtophys(ThreadContext *tc, Addr vaddr); - -inline Addr -PteAddr(Addr a) -{ - return (a & PteMask) << PteShift; -} - -} // namespace PowerISA - -#endif // __ARCH_POWER_VTOPHYS_HH__ - diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh index c648123a59..ca2a90b475 100644 --- a/src/arch/riscv/tlb.hh +++ b/src/arch/riscv/tlb.hh @@ -36,7 +36,6 @@ #include "arch/riscv/isa_traits.hh" #include "arch/riscv/pagetable.hh" #include "arch/riscv/utility.hh" -#include "arch/riscv/vtophys.hh" #include "base/statistics.hh" #include "mem/request.hh" #include "params/RiscvTLB.hh" diff --git a/src/arch/riscv/vtophys.hh b/src/arch/riscv/vtophys.hh deleted file mode 100644 index 7dcc7af2d0..0000000000 --- a/src/arch/riscv/vtophys.hh +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * Copyright (c) 2009 The University of Edinburgh - * Copyright (c) 2014-2015 Sven Karlsson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_RISCV_VTOPHYS_HH__ -#define __ARCH_RISCV_VTOPHYS_HH__ - -#include "arch/riscv/isa_traits.hh" -#include "arch/riscv/utility.hh" - -class ThreadContext; - -namespace RiscvISA -{ - -static inline Addr -vtophys(ThreadContext *tc, Addr vaddr) -{ - fatal("VTOPHYS: Unimplemented on RISC-V\n"); -} - -} // namespace RiscvISA - -#endif // __ARCH_RISCV_VTOPHYS_HH__ - diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 1caf8a09a6..4097ebba6c 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -48,7 +48,6 @@ if env['TARGET_ISA'] == 'sparc': Source('tlb.cc') Source('ua2005.cc') Source('utility.cc') - Source('vtophys.cc') SimObject('SparcFsWorkload.py') SimObject('SparcInterrupts.py') diff --git a/src/arch/sparc/fs_workload.cc b/src/arch/sparc/fs_workload.cc index 390c5ccd5a..4174bd5210 100644 --- a/src/arch/sparc/fs_workload.cc +++ b/src/arch/sparc/fs_workload.cc @@ -29,7 +29,6 @@ #include "arch/sparc/fs_workload.hh" #include "arch/sparc/faults.hh" -#include "arch/vtophys.hh" #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc index d0f3cd802a..cf91f3d9bd 100644 --- a/src/arch/sparc/remote_gdb.cc +++ b/src/arch/sparc/remote_gdb.cc @@ -124,7 +124,6 @@ #include #include -#include "arch/vtophys.hh" #include "base/intmath.hh" #include "base/remote_gdb.hh" #include "base/socket.hh" diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index 04fa7ad807..ac442cad5e 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -29,7 +29,6 @@ #include "arch/sparc/utility.hh" #include "arch/sparc/faults.hh" -#include "arch/sparc/vtophys.hh" #include "mem/fs_translating_port_proxy.hh" namespace SparcISA { diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc deleted file mode 100644 index 906d082d03..0000000000 --- a/src/arch/sparc/vtophys.cc +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/sparc/vtophys.hh" - -#include - -#include "arch/sparc/pagetable.hh" -#include "arch/sparc/tlb.hh" -#include "base/chunk_generator.hh" -#include "base/compiler.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/VtoPhys.hh" -#include "mem/port_proxy.hh" - -using namespace std; - -namespace SparcISA -{ - -Addr -vtophys(ThreadContext *tc, Addr addr) -{ - // Here we have many options and are really implementing something like - // a fill handler to find the address since there isn't a multilevel - // table for us to walk around. - // - // 1. We are currently hyperpriv, return the address unmodified - // 2. The mmu is off return(ra->pa) - // 3. We are currently priv, use ctx0* tsbs to find the page - // 4. We are not priv, use ctxN0* tsbs to find the page - // For all accesses we check the tlbs first since it's possible that - // long standing pages (e.g. locked kernel mappings) won't be in the tsb - uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); - - bool hpriv = bits(tlbdata,0,0); - // bool priv = bits(tlbdata,2,2); - bool addr_mask = bits(tlbdata,3,3); - bool data_real = !bits(tlbdata,5,5); - bool inst_real = !bits(tlbdata,4,4); - bool ctx_zero = bits(tlbdata,18,16) > 0; - int part_id = bits(tlbdata,15,8); - int pri_context = bits(tlbdata,47,32); - // int sec_context = bits(tlbdata,63,48); - - PortProxy &mem = tc->getPhysProxy(); - TLB* itb = dynamic_cast(tc->getITBPtr()); - TLB* dtb = dynamic_cast(tc->getDTBPtr()); - TlbEntry* tbe; - PageTableEntry pte; - Addr tsbs[4]; - Addr va_tag; - TteTag ttetag; - - if (hpriv) - return addr; - - if (addr_mask) - addr = addr & VAddrAMask; - - tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context , - false); - if (tbe) - goto foundtbe; - - tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context, - false); - if (tbe) - goto foundtbe; - - // We didn't find it in the tlbs, so lets look at the TSBs - dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs); - va_tag = bits(addr, 63, 22); - for (int x = 0; x < 4; x++) { - ttetag = betoh(mem.read(tsbs[x])); - if (ttetag.valid() && ttetag.va() == va_tag) { - uint64_t entry = mem.read(tsbs[x]) + sizeof(uint64_t); - // I think it's sun4v at least! - pte.populate(betoh(entry), PageTableEntry::sun4v); - DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n", - addr, pte.translate(addr)); - goto foundpte; - } - } - panic("couldn't translate %#x\n", addr); - - foundtbe: - pte = tbe->pte; - DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr, - pte.translate(addr)); - foundpte: - return pte.translate(addr); -} - -} // namespace SparcISA diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh deleted file mode 100644 index 33cefff2a8..0000000000 --- a/src/arch/sparc/vtophys.hh +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_SPARC_VTOPHYS_HH__ -#define __ARCH_SPARC_VTOPHYS_HH__ - -#include "arch/sparc/isa_traits.hh" - -class ThreadContext; - -namespace SparcISA -{ - -Addr vtophys(ThreadContext *tc, Addr vaddr); - -}; // namespace SparcISA - -#endif // __ARCH_SPARC_VTOPHYS_HH__ - diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 093b4ee1c6..bfe8d9d60a 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -70,7 +70,6 @@ if env['TARGET_ISA'] == 'x86': Source('tlb.cc') Source('types.cc') Source('utility.cc') - Source('vtophys.cc') SimObject('X86FsWorkload.py') SimObject('X86ISA.py') diff --git a/src/arch/x86/linux/fs_workload.cc b/src/arch/x86/linux/fs_workload.cc index 7e58b9e90a..4f83884587 100644 --- a/src/arch/x86/linux/fs_workload.cc +++ b/src/arch/x86/linux/fs_workload.cc @@ -37,7 +37,6 @@ #include "arch/x86/linux/fs_workload.hh" -#include "arch/vtophys.hh" #include "arch/x86/isa_traits.hh" #include "arch/x86/regs/int.hh" #include "base/trace.hh" diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index d655fa6ecf..b540be3467 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -54,7 +54,6 @@ #include "arch/x86/faults.hh" #include "arch/x86/pagetable.hh" #include "arch/x86/tlb.hh" -#include "arch/x86/vtophys.hh" #include "base/bitfield.hh" #include "base/trie.hh" #include "cpu/base.hh" diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc index 93848304c0..9603b90693 100644 --- a/src/arch/x86/remote_gdb.cc +++ b/src/arch/x86/remote_gdb.cc @@ -44,7 +44,6 @@ #include -#include "arch/vtophys.hh" #include "arch/x86/pagetable_walker.hh" #include "arch/x86/process.hh" #include "arch/x86/regs/int.hh" diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc index 4f824de619..3fe9ce4f1d 100644 --- a/src/arch/x86/stacktrace.cc +++ b/src/arch/x86/stacktrace.cc @@ -31,7 +31,6 @@ #include #include "arch/x86/isa_traits.hh" -#include "arch/x86/vtophys.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc deleted file mode 100644 index 5e07ddb3fb..0000000000 --- a/src/arch/x86/vtophys.cc +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/x86/vtophys.hh" - -#include - -#include "arch/x86/pagetable_walker.hh" -#include "arch/x86/tlb.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/VtoPhys.hh" - -using namespace std; - -Addr -X86ISA::vtophys(ThreadContext *tc, Addr vaddr) -{ - Walker *walker = dynamic_cast(tc->getDTBPtr())->getWalker(); - unsigned logBytes; - Addr addr = vaddr; - Fault fault = walker->startFunctional( - tc, addr, logBytes, BaseTLB::Read); - if (fault != NoFault) - panic("vtophys page walk returned fault\n"); - Addr masked_addr = vaddr & mask(logBytes); - Addr paddr = addr | masked_addr; - DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); - return paddr; -} diff --git a/src/arch/x86/vtophys.hh b/src/arch/x86/vtophys.hh deleted file mode 100644 index 51ce8eb2e9..0000000000 --- a/src/arch/x86/vtophys.hh +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_X86_VTOPHYS_HH__ -#define __ARCH_X86_VTOPHYS_HH__ - -#include "base/types.hh" - -class ThreadContext; - -namespace X86ISA -{ - -Addr vtophys(ThreadContext *tc, Addr vaddr); - -} - -#endif // __ARCH_X86_VTOPHYS_HH__