diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 43510e610e..98c29228b0 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -28,6 +28,7 @@
 #include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"
 
 #include "arch/arm/fastmodel/iris/cpu.hh"
+#include "arch/arm/regs/misc.hh"
 #include "base/logging.hh"
 #include "dev/arm/base_gic.hh"
 #include "sim/core.hh"
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc b/src/arch/arm/fastmodel/GIC/gic.cc
index 3133757f41..2830c83d55 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -70,7 +70,7 @@ SCGIC::Terminator::sendTowardsCPU(uint8_t len, const uint8_t *data)
 
 SCGIC::SCGIC(const SCFastModelGICParams &params,
              sc_core::sc_module_name _name)
-    : scx_evs_GIC(_name)
+    : scx_evs_GIC(_name), _params(params)
 {
     signalInterrupt.bind(signal_interrupt);
 
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh b/src/arch/arm/fastmodel/GIC/gic.hh
index 33997fd668..b283108dd0 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -81,6 +81,7 @@ class SCGIC : public scx_evs_GIC
     };
 
     std::unique_ptr<Terminator> terminator;
+    const SCFastModelGICParams &_params;
 
   public:
     SCGIC(const SCFastModelGICParams &p) : SCGIC(p, p.name.c_str()) {}
diff --git a/src/arch/arm/fastmodel/iris/isa.cc b/src/arch/arm/fastmodel/iris/isa.cc
index 4aac71fa1d..9312d4ea39 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -28,8 +28,8 @@
 #include "arch/arm/fastmodel/iris/isa.hh"
 
 #include "arch/arm/regs/misc.hh"
+#include "base/logging.hh"
 #include "cpu/thread_context.hh"
-#include "params/IrisISA.hh"
 #include "sim/serialize.hh"
 
 void
@@ -40,3 +40,9 @@ Iris::ISA::serialize(CheckpointOut &cp) const
         miscRegs[i] = tc->readMiscRegNoEffect(i);
     SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS);
 }
+
+void
+Iris::ISA::copyRegsFrom(ThreadContext *src)
+{
+    panic("copyRegsFrom not implemented");
+}
diff --git a/src/arch/arm/fastmodel/iris/isa.hh b/src/arch/arm/fastmodel/iris/isa.hh
index a7ae7b52d6..9b2828cae1 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -39,13 +39,15 @@ class ISA : public BaseISA
   public:
     ISA(const Params &p) : BaseISA(p) {}
 
-    void serialize(CheckpointOut &cp) const;
+    void serialize(CheckpointOut &cp) const override;
+
+    void copyRegsFrom(ThreadContext *src) override;
 
     bool
     inUserMode() const override
     {
-        CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-        return ::inUserMode(cpsr);
+        ArmISA::CPSR cpsr = tc->readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
+        return ArmISA::inUserMode(cpsr);
     }
 };
 
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc
index 239259245b..0219ab51eb 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -670,7 +670,7 @@ ThreadContext::readVecReg(const RegId &reg_id) const
     call().resource_read(_instId, result, vecRegIds.at(idx));
     size_t data_size = result.data.size() * (sizeof(*result.data.data()));
     size_t size = std::min(data_size, reg.size());
-    memcpy(reg.raw_ptr<void>(), (void *)result.data.data(), size);
+    memcpy(reg.as<uint8_t>(), (void *)result.data.data(), size);
 
     return reg;
 }
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index 5c8d82f4fd..22ea42b4ce 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -32,6 +32,7 @@
 #include <map>
 #include <memory>
 
+#include "arch/arm/regs/vec.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "iris/IrisInstance.h"
@@ -276,21 +277,22 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecRegContainer &readVecReg(const RegId &reg) const override;
-    VecRegContainer &
+    const ArmISA::VecRegContainer &readVecReg(const RegId &reg) const override;
+    ArmISA::VecRegContainer &
     getWritableVecReg(const RegId &reg) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecElem &
+    const ArmISA::VecElem &
     readVecElem(const RegId &reg) const override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecPredRegContainer &readVecPredReg(const RegId &reg) const override;
-    VecPredRegContainer &
+    const ArmISA::VecPredRegContainer &
+        readVecPredReg(const RegId &reg) const override;
+    ArmISA::VecPredRegContainer &
     getWritableVecPredReg(const RegId &reg) override
     {
         panic("%s not implemented.", __FUNCTION__);
@@ -311,20 +313,20 @@ class ThreadContext : public ::ThreadContext
     }
 
     void
-    setVecReg(const RegId &reg, const VecRegContainer &val) override
+    setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
 
     void
-    setVecElem(const RegId& reg, const VecElem& val) override
+    setVecElem(const RegId& reg, const ArmISA::VecElem& val) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
 
     void
     setVecPredReg(const RegId &reg,
-                  const VecPredRegContainer &val) override
+                  const ArmISA::VecPredRegContainer &val) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
@@ -403,38 +405,40 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
-    VecRegContainer &
+    const ArmISA::VecRegContainer &readVecRegFlat(RegIndex idx) const override;
+    ArmISA::VecRegContainer &
     getWritableVecRegFlat(RegIndex idx) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
     void
-    setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
+    setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecElem&
+    const ArmISA::VecElem&
     readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
     void
     setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
-                   const VecElem &val) override
+                   const ArmISA::VecElem &val) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const override;
-    VecPredRegContainer &
+    const ArmISA::VecPredRegContainer &
+        readVecPredRegFlat(RegIndex idx) const override;
+    ArmISA::VecPredRegContainer &
     getWritableVecPredRegFlat(RegIndex idx) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
     void
-    setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) override
+    setVecPredRegFlat(RegIndex idx,
+            const ArmISA::VecPredRegContainer &val) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }