arch-riscv: Enable support for riscv 32-bit in SE mode.

This patch splits up the riscv SE mode support for 32 and 64-bit.
A future patch will add support for decoding rv32 instructions.

Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15355
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

src/base/loader/elf_object.cc

@@ -112,7 +112,7 @@ ElfObject::tryFile(const std::string &fname, size_t len, uint8_t *data,
                ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
         arch = Arm64;
     } else if (ehdr.e_machine == EM_RISCV) {
-        arch = Riscv;
+        arch = (ehdr.e_ident[EI_CLASS] == ELFCLASS64) ? Riscv64 : Riscv32;
     } else if (ehdr.e_machine == EM_PPC &&
                ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
         arch = Power;

src/base/loader/object_file.hh

@@ -57,7 +57,8 @@ class ObjectFile
         Arm,
         Thumb,
         Power,
-        Riscv
+        Riscv64,
+        Riscv32
     };
 
     enum OpSys {