diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index dc54ec2d5a..025f75755d 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -129,9 +129,6 @@ let {{
     def vectorRegElem(elem, ext = 'sf', zeroing = False):
         return (elem, ext, zeroing)
 
-    def floatReg(idx):
-        return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
-
     def intReg(idx):
         return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                 maybePCRead, maybePCWrite)