Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. --HG-- extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d
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@@ -56,8 +56,9 @@ void UnimpFault::invoke(ThreadContext * tc)
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{
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panic("Unimpfault: %s\n", panicStr.c_str());
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}
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#if !FULL_SYSTEM
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void PageTableFault::invoke(ThreadContext *tc)
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void GenericPageTableFault::invoke(ThreadContext *tc)
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{
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Process *p = tc->getProcessPtr();
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@@ -65,4 +66,9 @@ void PageTableFault::invoke(ThreadContext *tc)
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panic("Page table fault when accessing virtual address %#x\n", vaddr);
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}
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void GenericAlignmentFault::invoke(ThreadContext *tc)
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{
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panic("Alignment fault when accessing virtual address %#x\n", vaddr);
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}
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#endif
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@@ -77,13 +77,23 @@ class UnimpFault : public FaultBase
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};
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#if !FULL_SYSTEM
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class PageTableFault : public FaultBase
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class GenericPageTableFault : public FaultBase
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{
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private:
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Addr vaddr;
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public:
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FaultName name() const {return "M5 page table fault";}
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PageTableFault(Addr va) : vaddr(va) {}
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FaultName name() const {return "Generic page table fault";}
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GenericPageTableFault(Addr va) : vaddr(va) {}
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void invoke(ThreadContext * tc);
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};
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class GenericAlignmentFault : public FaultBase
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{
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private:
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Addr vaddr;
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public:
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FaultName name() const {return "Generic alignment fault";}
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GenericAlignmentFault(Addr va) : vaddr(va) {}
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void invoke(ThreadContext * tc);
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};
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#endif
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@@ -34,21 +34,17 @@
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#include "sim/tlb.hh"
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Fault
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GenericITB::translate(RequestPtr &req, ThreadContext *tc)
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GenericTLBBase::translate(RequestPtr req, ThreadContext * tc)
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{
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#if FULL_SYSTEM
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panic("Generic ITB translation shouldn't be used in full system mode.\n");
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panic("Generic translation shouldn't be used in full system mode.\n");
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#else
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return tc->getProcessPtr()->pTable->translate(req);
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Process * p = tc->getProcessPtr();
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Fault fault = p->pTable->translate(req);
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if(fault != NoFault)
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return fault;
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return NoFault;
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#endif
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}
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Fault
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GenericDTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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{
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#if FULL_SYSTEM
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panic("Generic DTB translation shouldn't be used in full system mode.\n");
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#else
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return tc->getProcessPtr()->pTable->translate(req);
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#endif
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};
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@@ -31,36 +31,64 @@
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#ifndef __SIM_TLB_HH__
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#define __SIM_TLB_HH__
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#include "base/misc.hh"
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#include "mem/request.hh"
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#include "sim/sim_object.hh"
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#include "sim/faults.hh"
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#include "sim/sim_object.hh"
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class ThreadContext;
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class Packet;
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class GenericTLB : public SimObject
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class GenericTLBBase : public SimObject
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{
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protected:
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GenericTLBBase(const std::string &name) : SimObject(name)
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{}
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Fault translate(RequestPtr req, ThreadContext *tc);
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};
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template <bool doSizeCheck=true, bool doAlignmentCheck=true>
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class GenericTLB : public GenericTLBBase
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{
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public:
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GenericTLB(const std::string &name) : SimObject(name)
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GenericTLB(const std::string &name) : GenericTLBBase(name)
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{}
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Fault translate(RequestPtr req, ThreadContext *tc, bool=false)
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{
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Fault fault = GenericTLBBase::translate(req, tc);
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if (fault != NoFault)
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return fault;
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typeof(req->getSize()) size = req->getSize();
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Addr paddr = req->getPaddr();
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if(doSizeCheck && !isPowerOf2(size))
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panic("Invalid request size!\n");
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if (doAlignmentCheck && ((size - 1) & paddr))
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return Fault(new GenericAlignmentFault(paddr));
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return NoFault;
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}
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};
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template <bool doSizeCheck=true, bool doAlignmentCheck=true>
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class GenericITB : public GenericTLB<doSizeCheck, doAlignmentCheck>
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{
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public:
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GenericITB(const std::string &name) :
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GenericTLB<doSizeCheck, doAlignmentCheck>(name)
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{}
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};
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class GenericITB : public GenericTLB
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template <bool doSizeCheck=true, bool doAlignmentCheck=true>
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class GenericDTB : public GenericTLB<doSizeCheck, doAlignmentCheck>
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{
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public:
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GenericITB(const std::string &name) : GenericTLB(name)
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GenericDTB(const std::string &name) :
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GenericTLB<doSizeCheck, doAlignmentCheck>(name)
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{}
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Fault translate(RequestPtr &req, ThreadContext *tc);
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};
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class GenericDTB : public GenericTLB
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{
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public:
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GenericDTB(const std::string &name) : GenericTLB(name)
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{}
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Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
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};
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#endif // __ARCH_SPARC_TLB_HH__
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