Fix some more mem leaks, still some left
Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
--HG--
extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
This commit is contained in:
57
src/mem/cache/base_cache.cc
vendored
57
src/mem/cache/base_cache.cc
vendored
@@ -45,6 +45,7 @@ BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
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{
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blocked = false;
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cshrRetry = NULL;
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waitingOnRetry = false;
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//Start ports at null if more than one is created we should panic
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//cpuSidePort = NULL;
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//memSidePort = NULL;
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@@ -113,25 +114,30 @@ void
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BaseCache::CachePort::recvRetry()
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{
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Packet *pkt;
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assert(waitingOnRetry);
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if (!drainList.empty()) {
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//We have some responses to drain first
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bool result = true;
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while (result && !drainList.empty()) {
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result = sendTiming(drainList.front());
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if (result)
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drainList.pop_front();
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if (sendTiming(drainList.front())) {
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drainList.pop_front();
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if (!drainList.empty() ||
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!isCpuSide && cache->doMasterRequest() ||
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isCpuSide && cache->doSlaveRequest()) {
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BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
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reqCpu->schedule(curTick + 1);
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}
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waitingOnRetry = false;
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}
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if (!result) return;
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}
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else if (!isCpuSide)
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{
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if (!cache->doMasterRequest()) return;
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assert(cache->doMasterRequest());
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pkt = cache->getPacket();
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MSHR* mshr = (MSHR*)pkt->senderState;
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bool success = sendTiming(pkt);
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DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
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pkt->getAddr(), success ? "succesful" : "unsuccesful");
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cache->sendResult(pkt, mshr, success);
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waitingOnRetry = !success;
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if (success && cache->doMasterRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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@@ -140,12 +146,14 @@ BaseCache::CachePort::recvRetry()
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reqCpu->schedule(curTick + 1);
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}
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}
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else if (cshrRetry)
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else
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{
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assert(cshrRetry);
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//pkt = cache->getCoherencePacket();
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//We save the packet, no reordering on CSHRS
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pkt = cshrRetry;
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bool success = sendTiming(pkt);
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waitingOnRetry = !success;
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if (success && cache->doSlaveRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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@@ -154,7 +162,6 @@ BaseCache::CachePort::recvRetry()
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reqCpu->schedule(curTick + 1);
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cshrRetry = NULL;
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}
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}
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return;
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}
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@@ -198,23 +205,22 @@ BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
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void
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BaseCache::CacheEvent::process()
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{
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if (!cachePort->drainList.empty()) {
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//We have some responses to drain first
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bool result = true;
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while (result && !cachePort->drainList.empty()) {
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result = cachePort->sendTiming(cachePort->drainList.front());
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if (result)
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cachePort->drainList.pop_front();
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}
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if (!result) return;
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}
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if (!pkt)
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{
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if (!cachePort->isCpuSide)
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if (cachePort->waitingOnRetry) return;
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//We have some responses to drain first
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if (!cachePort->drainList.empty()) {
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if (cachePort->sendTiming(cachePort->drainList.front())) {
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cachePort->drainList.pop_front();
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if (!cachePort->drainList.empty() ||
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!cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
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cachePort->isCpuSide && cachePort->cache->doSlaveRequest())
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this->schedule(curTick + 1);
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}
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else cachePort->waitingOnRetry = true;
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}
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else if (!cachePort->isCpuSide)
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{
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//For now, doMasterRequest somehow is still getting set
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if (!cachePort->cache->doMasterRequest()) return;
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//MSHR
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pkt = cachePort->cache->getPacket();
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MSHR* mshr = (MSHR*) pkt->senderState;
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@@ -222,6 +228,7 @@ BaseCache::CacheEvent::process()
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DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
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pkt->getAddr(), success ? "succesful" : "unsuccesful");
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cachePort->cache->sendResult(pkt, mshr, success);
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cachePort->waitingOnRetry = !success;
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if (success && cachePort->cache->doMasterRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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@@ -237,6 +244,7 @@ BaseCache::CacheEvent::process()
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if (!success) {
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//Need to send on a retry
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cachePort->cshrRetry = pkt;
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cachePort->waitingOnRetry = true;
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}
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else if (cachePort->cache->doSlaveRequest())
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{
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@@ -255,12 +263,13 @@ BaseCache::CacheEvent::process()
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pkt->result = Packet::Success;
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pkt->makeTimingResponse();
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if (!cachePort->drainList.empty()) {
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//Already blocked waiting for bus, just append
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//Already have a list, just append
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cachePort->drainList.push_back(pkt);
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}
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else if (!cachePort->sendTiming(pkt)) {
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//It failed, save it to list of drain events
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cachePort->drainList.push_back(pkt);
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cachePort->waitingOnRetry = true;
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}
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}
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