misc: Merged release-staging-v19.0.0.0 into develop

CONTRIBUTING.md

@@ -485,28 +485,30 @@ follows:
 
 1. Developers will be notified, via the gem5-dev mailing list, that a new
 release of gem5 will occur. This should be no sooner than 2 weeks prior to the
-expected release date. This gives time for developers to ensure their changes
-for the next release are submitted to the develop branch.
+creation of the staging branch (the first step in releasing a new version of
+gem5). This gives time for developers to ensure their changes for the next
+release are submitted to the develop branch.
 2. When a release is ready, a new staging branch shall be created by a project
-maintainer, from develop, with the name "release-staging-{VERSION}".
-The gem5-dev mailing list will be notified that, unless justifiable objections
-are made, the staging branch will be merged into the master branch within the
-next week, thus marking the new release.
+maintainer, from develop, with the name "release-staging-{VERSION}". The
+gem5-dev mailing list will be notified that the staging branch will be merged
+into the master branch after two weeks, thus marking the new release.
 3. The staging branch will have the full suite of gem5 tests run on it to
 ensure all tests pass and the to-be-released code is in a decent state.
-4. If reasonable concerns about the state of the staging branch are made by
-members of the gem5 community, then time shall be given for project
-contributors to rectify these concerns on the develop branch. After these
-changes have been incorporated, the develop branch will be re-merged into the
-staging branch. The staging branch will be re-evaluated via the tests, and the
-gem5 community informed of the changes with additional time given for more
-feedback on the new release.
+4. If a user submits a changeset to the staging branch, it will be considered
+and undergo the standard Gerrit review process. However, only alterations that
+cannot wait until the following release will be accepted for submission into
+the branch (i.e., submissions to the staging branch for "last minute"
+inclusions to the release should be of a high priority, such as a critical bug
+fix). The project maintainers will use their discretion in deciding whether a
+change may be submitted directly to the staging branch. All other submissions
+to gem5 will continue to be made to the develop branch. Patches submitted
+into the staging branch do not need to be re-added to the develop branch.
 5. Once signed off by members of the PMC the staging branch shall be merged
-into the master branch, and the staging branch deleted.
+into the master and develop branch. The staging branch will then be deleted.
 6. The master branch shall be tagged with the correct version number for that
 release. gem5 conforms to a "v{YY}.{MAJOR}.{MINOR}.{HOTFIX}" versioning system.
 E.g., the first major release of 2022 will be "v22.0.0.0", followed by
-"v22.1.0.0". All the releases (with the exemption hotfixes) are considered
+"v22.1.0.0". All the releases (with the exception of hotfixes) are considered
 major releases. For the meantime, there are no minor releases though we keep
 the minor release numbers in case this policy changes in the future.
 7. The gem5-dev and gem5-user mailing lists shall be notified of the new gem5

src/Doxyfile

@@ -31,7 +31,7 @@ PROJECT_NAME           = gem5
 # This could be handy for archiving the generated documentation or 
 # if some version control system is used.
 
-PROJECT_NUMBER         = 
+PROJECT_NUMBER         = v19.0.0.0
 
 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) 
 # base path where the generated documentation will be put. 

src/arch/arm/kvm/arm_cpu.cc

@@ -43,6 +43,7 @@
 #include <cerrno>
 #include <memory>
 
+#include "arch/arm/interrupts.hh"
 #include "arch/registers.hh"
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
@@ -268,8 +269,9 @@ ArmKvmCPU::startup()
 Tick
 ArmKvmCPU::kvmRun(Tick ticks)
 {
-    bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-    bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+    auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
+    const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+    const bool simIRQ(interrupt->checkRaw(INT_IRQ));
 
     if (fiqAsserted != simFIQ) {
         fiqAsserted = simFIQ;

src/arch/arm/kvm/base_cpu.cc

@@ -39,6 +39,7 @@
 
 #include <linux/kvm.h>
 
+#include "arch/arm/interrupts.hh"
 #include "debug/KvmInt.hh"
 #include "params/BaseArmKvmCPU.hh"
 
@@ -86,8 +87,9 @@ BaseArmKvmCPU::startup()
 Tick
 BaseArmKvmCPU::kvmRun(Tick ticks)
 {
-    const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-    const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+    auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
+    const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+    const bool simIRQ(interrupt->checkRaw(INT_IRQ));
 
     if (!vm.hasKernelIRQChip()) {
         if (fiqAsserted != simFIQ) {

src/arch/arm/miscregs.cc

@@ -3703,8 +3703,9 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_HTPIDR)
       .hyp().monNonSecure();
     InitReg(MISCREG_CNTFRQ)
-      .unverifiable()
-      .reads(1).mon();
+      .reads(1)
+      .highest(system)
+      .privSecureWrite(aarch32EL3);
     InitReg(MISCREG_CNTKCTL)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_CNTP_TVAL)
@@ -4449,7 +4450,9 @@ ISA::initializeMiscRegMetadata()
       .allPrivileges().exceptUserMode()
       .mapsTo(MISCREG_CNTKCTL);
     InitReg(MISCREG_CNTFRQ_EL0)
-      .reads(1).mon()
+      .reads(1)
+      .highest(system)
+      .privSecureWrite(aarch32EL3)
       .mapsTo(MISCREG_CNTFRQ);
     InitReg(MISCREG_CNTPCT_EL0)
       .reads(1)

src/dev/arm/RealView.py

@@ -1075,9 +1075,7 @@ Interrupts:
             self._attach_device(dev, bus, dma_ports)
             self.smmu.connect(dev, bus)
 
-    def setupBootLoader(self, cur_sys, loc, boot_loader=None):
-        if boot_loader is None:
-            boot_loader = [ loc('boot.arm64'), loc('boot.arm') ]
+    def setupBootLoader(self, cur_sys, boot_loader):
         super(VExpress_GEM5_Base, self).setupBootLoader(
                 cur_sys, boot_loader, 0x8000000, 0x80000000)
 
@@ -1109,6 +1107,12 @@ class VExpress_GEM5_V1_Base(VExpress_GEM5_Base):
         Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
     ]
 
+    def setupBootLoader(self, cur_sys, loc, boot_loader=None):
+        if boot_loader is None:
+            boot_loader = [ loc('boot.arm64'), loc('boot.arm') ]
+        super(VExpress_GEM5_V1_Base, self).setupBootLoader(
+                cur_sys, boot_loader)
+
     def _on_chip_devices(self):
         return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [
                 self.gic, self.vgic, self.gicv2m,

src/sim/pseudo_inst.hh

@@ -75,7 +75,10 @@ struct Argument<PseudoInstABI, uint64_t>
     static uint64_t
     get(ThreadContext *tc, PseudoInstABI::Position &position)
     {
-        return TheISA::getArgument(tc, position, sizeof(uint64_t), false);
+        uint64_t result = TheISA::getArgument(tc, position, sizeof(uint64_t),
+                                              false);
+        position++;
+        return result;
     }
 };