diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 039717a8b7..10dfa5cb74 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1928,8 +1928,15 @@ faultSctlr2EL1(const MiscRegLUTEntry &entry,
     if (HaveExt(tc, ArmExtension::FEAT_SCTLR2)) {
         const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
         const HCRX hcrx = tc->readMiscReg(MISCREG_HCRX_EL2);
-        if (auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::sctlrEL1>(entry, tc, inst);
-            fault != NoFault) {
+        if (
+                auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::sctlrEL1>
+                (
+                    entry,
+                    tc,
+                    inst
+                );
+                fault != NoFault
+        ) {
             return fault;
         } else if (EL2Enabled(tc) && (!isHcrxEL2Enabled(tc) || !hcrx.sctlr2En)) {
             return inst.generateTrap(EL2);
@@ -1988,8 +1995,15 @@ faultTcr2EL1(const MiscRegLUTEntry &entry,
     if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
         const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
         const HCRX hcrx = tc->readMiscReg(MISCREG_HCRX_EL2);
-        if (auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::tcrEL1>(entry, tc, inst);
-            fault != NoFault) {
+        if (
+                auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::sctlrEL1>
+                (
+                    entry,
+                    tc,
+                    inst
+                );
+                fault != NoFault
+        ) {
             return fault;
         } else if (EL2Enabled(tc) && (!isHcrxEL2Enabled(tc) || !hcrx.tcr2En)) {
             return inst.generateTrap(EL2);
@@ -4488,7 +4502,8 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_ID_AA64MMFR1_EL1)
       .reset([p,release=release](){
           AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
-          mmfr1_el1.vmidbits = release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0;
+          mmfr1_el1.vmidbits =
+            release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0;
           mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
           mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0;
           mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
@@ -4513,7 +4528,8 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_ID_AA64MMFR3_EL1)
       .reset([p,release=release](){
           AA64MMFR3 mmfr3_el1 = 0;
-          mmfr3_el1.sctlrx = release->has(ArmExtension::FEAT_SCTLR2) ? 0x1 : 0x0;
+          mmfr3_el1.sctlrx =
+            release->has(ArmExtension::FEAT_SCTLR2) ? 0x1 : 0x0;
           mmfr3_el1.tcrx = release->has(ArmExtension::FEAT_TCR2) ? 0x1 : 0x0;
           return mmfr3_el1;
       }())