diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5c8c7436de..32103514cf 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -88,10 +88,10 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
 {
     _regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
     _regClasses.emplace_back(0);
-    _regClasses.emplace_back(NumVecRegs);
+    _regClasses.emplace_back(NumVecRegs, -1, sizeof(VecRegContainer));
     _regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
             vecRegElemClassOps);
-    _regClasses.emplace_back(NumVecPredRegs);
+    _regClasses.emplace_back(NumVecPredRegs, -1, sizeof(VecPredRegContainer));
     _regClasses.emplace_back(NUM_CCREGS);
     _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);
 
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index ab3e8f9889..5664bc31be 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -41,12 +41,11 @@
 #ifndef __CPU__REG_CLASS_HH__
 #define __CPU__REG_CLASS_HH__
 
-#include <cassert>
 #include <cstddef>
 #include <string>
 
+#include "base/intmath.hh"
 #include "base/types.hh"
-#include "config/the_isa.hh"
 
 namespace gem5
 {
@@ -97,22 +96,32 @@ class RegClass
   private:
     size_t _numRegs;
     const RegIndex _zeroReg;
+    size_t _regBytes;
+    // This is how much to shift an index by to get an offset of a register in
+    // a register file from the register index, which would otherwise need to
+    // be calculated with a multiply.
+    size_t _regShift;
 
     static inline DefaultRegClassOps defaultOps;
     RegClassOps *_ops = &defaultOps;
 
   public:
-    RegClass(size_t num_regs, RegIndex new_zero=-1) :
-        _numRegs(num_regs), _zeroReg(new_zero)
+    RegClass(size_t num_regs, RegIndex new_zero=-1,
+            size_t reg_bytes=sizeof(RegVal)) :
+        _numRegs(num_regs), _zeroReg(new_zero), _regBytes(reg_bytes),
+        _regShift(ceilLog2(reg_bytes))
     {}
-    RegClass(size_t num_regs, RegClassOps &new_ops, RegIndex new_zero=-1) :
-        RegClass(num_regs, new_zero)
+    RegClass(size_t num_regs, RegClassOps &new_ops, RegIndex new_zero=-1,
+            size_t reg_bytes=sizeof(RegVal)) :
+        RegClass(num_regs, new_zero, reg_bytes)
     {
         _ops = &new_ops;
     }
 
     size_t numRegs() const { return _numRegs; }
     RegIndex zeroReg() const { return _zeroReg; }
+    size_t regBytes() const { return _regBytes; }
+    size_t regShift() const { return _regShift; }
 
     std::string regName(const RegId &id) const { return _ops->regName(id); }
 };