misc: Adopt the gem5 namespace

Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/BadDevice.py

@@ -30,4 +30,6 @@ from m5.objects.Device import BasicPioDevice
 class BadDevice(BasicPioDevice):
     type = 'BadDevice'
     cxx_header = "dev/baddev.hh"
+    cxx_class = 'gem5::BadDevice'
+
     devicename = Param.String("Name of device to error on")

src/dev/Device.py

@@ -45,7 +45,9 @@ from m5.objects.ClockedObject import ClockedObject
 class PioDevice(ClockedObject):
     type = 'PioDevice'
     cxx_header = "dev/io_device.hh"
+    cxx_class = 'gem5::PioDevice'
     abstract = True
+
     pio = ResponsePort("Programmed I/O port")
     system = Param.System(Parent.any, "System this device is part of")
 
@@ -71,14 +73,18 @@ class PioDevice(ClockedObject):
 class BasicPioDevice(PioDevice):
     type = 'BasicPioDevice'
     cxx_header = "dev/io_device.hh"
+    cxx_class = 'gem5::BasicPioDevice'
     abstract = True
+
     pio_addr = Param.Addr("Device Address")
     pio_latency = Param.Latency('100ns', "Programmed IO latency")
 
 class DmaDevice(PioDevice):
     type = 'DmaDevice'
     cxx_header = "dev/dma_device.hh"
+    cxx_class = 'gem5::DmaDevice'
     abstract = True
+
     dma = RequestPort("DMA port")
 
     _iommu = None
@@ -105,6 +111,8 @@ class DmaDevice(PioDevice):
 class IsaFake(BasicPioDevice):
     type = 'IsaFake'
     cxx_header = "dev/isa_fake.hh"
+    cxx_class = 'gem5::IsaFake'
+
     pio_size = Param.Addr(0x8, "Size of address range")
     ret_data8 = Param.UInt8(0xFF, "Default data to return")
     ret_data16 = Param.UInt16(0xFFFF, "Default data to return")

src/dev/Platform.py

@@ -32,6 +32,8 @@ class Platform(SimObject):
     type = 'Platform'
     abstract = True
     cxx_header = "dev/platform.hh"
+    cxx_class = 'gem5::Platform'
+
     system = Param.System(Parent.any, "system")
 
     # for platforms using device trees to set properties of CPU nodes

src/dev/amdgpu/AMDGPU.py

@@ -43,6 +43,7 @@ from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar
 class AMDGPUDevice(PciDevice):
     type = 'AMDGPUDevice'
     cxx_header = "dev/amdgpu/amdgpu_device.hh"
+    cxx_class = 'gem5::AMDGPUDevice'
 
     # IDs for AMD Vega 10
     VendorID = 0x1002

src/dev/amdgpu/amdgpu_device.cc

@@ -42,6 +42,9 @@
 #include "sim/byteswap.hh"
 #include "sim/sim_exit.hh"
 
+namespace gem5
+{
+
 AMDGPUDevice::AMDGPUDevice(const AMDGPUDeviceParams &p)
     : PciDevice(p), checkpoint_before_mmios(p.checkpoint_before_mmios),
       init_interrupt_count(0)
@@ -274,3 +277,5 @@ AMDGPUDevice::unserialize(CheckpointIn &cp)
     // Unserialize the PciDevice base class
     PciDevice::unserialize(cp);
 }
+
+} // namespace gem5

src/dev/amdgpu/amdgpu_device.hh

@@ -42,6 +42,9 @@
 #include "dev/pci/device.hh"
 #include "params/AMDGPUDevice.hh"
 
+namespace gem5
+{
+
 /* Names of BARs used by the device. */
 constexpr int FRAMEBUFFER_BAR = 0;
 constexpr int DOORBELL_BAR = 2;
@@ -128,4 +131,6 @@ class AMDGPUDevice : public PciDevice
     void unserialize(CheckpointIn &cp) override;
 };
 
+} // namespace gem5
+
 #endif // __DEV_AMDGPU_AMDGPU_DEVICE_HH__

src/dev/amdgpu/mmio_reader.cc

@@ -39,6 +39,8 @@
 #include "debug/AMDGPUDevice.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
 
 void
 AMDMMIOReader::readMMIOTrace(std::string trace_file)
@@ -113,3 +115,5 @@ AMDMMIOReader::writeFromTrace(PacketPtr pkt, int barnum, Addr offset)
         trace_cur_index++;
     }
 }
+
+} // namespace gem5

src/dev/amdgpu/mmio_reader.hh

@@ -44,6 +44,9 @@
 #include "base/logging.hh"
 #include "mem/packet.hh"
 
+namespace gem5
+{
+
 /**
  * Helper class to read Linux kernel MMIO trace from amdgpu modprobes. This
  * class is used rather than implementing MMIOs in code as it is easier to
@@ -246,4 +249,6 @@ class AMDMMIOReader
     void writeFromTrace(PacketPtr pkt, int barnum, Addr offset);
 };
 
-#endif /* __DEV_AMDGPU_MMIO_READER_HH__ */
+} // namespace gem5
+
+#endif // __DEV_AMDGPU_MMIO_READER_HH__

src/dev/arm/AbstractNVM.py

@@ -41,3 +41,4 @@ class AbstractNVM(SimObject):
     type = 'AbstractNVM'
     abstract = True
     cxx_header = "dev/arm/abstract_nvm.hh"
+    cxx_class = 'gem5::AbstractNVM'

src/dev/arm/Display.py

@@ -40,6 +40,7 @@ from m5.util.fdthelper import *
 class Display(SimObject):
     type = 'Display'
     cxx_header = "dev/arm/display.hh"
+    cxx_class = 'gem5::Display'
     clock_frequency = Param.Unsigned("clock-frequency property")
     hactive = Param.Unsigned("hactive property")
     vactive = Param.Unsigned("vactive property")

src/dev/arm/Doorbell.py

@@ -40,5 +40,6 @@ class Doorbell(SimObject):
     type = 'Doorbell'
     abstract = True
     cxx_header = "dev/arm/doorbell.hh"
+    cxx_class = 'gem5::Doorbell'
     set_address = Param.Addr("Doorbell set address")
     clear_address = Param.Addr("Doorbell clear address")

src/dev/arm/EnergyCtrl.py

@@ -42,6 +42,7 @@ from m5.util.fdthelper import *
 class EnergyCtrl(BasicPioDevice):
     type = 'EnergyCtrl'
     cxx_header = "dev/arm/energy_ctrl.hh"
+    cxx_class = 'gem5::EnergyCtrl'
     dvfs_handler = Param.DVFSHandler(Parent.dvfs_handler, "DVFS handler")
 
     def generateDeviceTree(self, state):

src/dev/arm/FlashDevice.py

@@ -47,6 +47,7 @@ class DataDistribution(Enum): vals = ['sequential', 'stripe']
 class FlashDevice(AbstractNVM):
     type = 'FlashDevice'
     cxx_header = "dev/arm/flash_device.hh"
+    cxx_class = 'gem5::FlashDevice'
     # default blocksize is 128 KiB.This seems to be the most common size in
     # mobile devices (not the image blocksize)
     blk_size = Param.MemorySize("128KiB", "Size of one disk block")

src/dev/arm/GenericTimer.py

@@ -52,6 +52,7 @@ Reference:
 
     type = 'SystemCounter'
     cxx_header = "dev/arm/generic_timer.hh"
+    cxx_class = 'gem5::SystemCounter'
 
     # Maximum of 1004 frequency entries, including end marker
     freqs = VectorParam.UInt32([0x01800000], "Frequencies available for the "
@@ -77,6 +78,7 @@ Reference:
 
     type = 'GenericTimer'
     cxx_header = "dev/arm/generic_timer.hh"
+    cxx_class = 'gem5::GenericTimer'
 
     _freq_in_dtb = False
 
@@ -129,6 +131,7 @@ Reference:
 
     type = 'GenericTimerFrame'
     cxx_header = "dev/arm/generic_timer.hh"
+    cxx_class = 'gem5::GenericTimerFrame'
 
     _frame_num = 0
 
@@ -173,6 +176,7 @@ Reference:
 
     type = 'GenericTimerMem'
     cxx_header = "dev/arm/generic_timer.hh"
+    cxx_class = 'gem5::GenericTimerMem'
 
     _freq_in_dtb = False
 

src/dev/arm/Gic.py

@@ -46,6 +46,7 @@ class BaseGic(PioDevice):
     type = 'BaseGic'
     abstract = True
     cxx_header = "dev/arm/base_gic.hh"
+    cxx_class = 'gem5::BaseGic'
 
     # Used for DTB autogeneration
     _state = FdtState(addr_cells=0, interrupt_cells=3)
@@ -96,7 +97,7 @@ class ArmInterruptType(ScopedEnum):
 class ArmInterruptPin(SimObject):
     type = 'ArmInterruptPin'
     cxx_header = "dev/arm/base_gic.hh"
-    cxx_class = "ArmInterruptPinGen"
+    cxx_class = "gem5::ArmInterruptPinGen"
     abstract = True
 
     platform = Param.Platform(Parent.any, "Platform with interrupt controller")
@@ -107,7 +108,7 @@ class ArmInterruptPin(SimObject):
 class ArmSPI(ArmInterruptPin):
     type = 'ArmSPI'
     cxx_header = "dev/arm/base_gic.hh"
-    cxx_class = "ArmSPIGen"
+    cxx_class = "gem5::ArmSPIGen"
 
     _LINUX_ID = 0
 
@@ -124,7 +125,7 @@ class ArmSPI(ArmInterruptPin):
 class ArmPPI(ArmInterruptPin):
     type = 'ArmPPI'
     cxx_header = "dev/arm/base_gic.hh"
-    cxx_class = "ArmPPIGen"
+    cxx_class = "gem5::ArmPPIGen"
 
     _LINUX_ID = 1
 
@@ -141,13 +142,14 @@ class ArmPPI(ArmInterruptPin):
 class ArmSigInterruptPin(ArmInterruptPin):
     type = 'ArmSigInterruptPin'
     cxx_header = "dev/arm/base_gic.hh"
-    cxx_class = "ArmSigInterruptPinGen"
+    cxx_class = "gem5::ArmSigInterruptPinGen"
 
     irq = IntSourcePin('Interrupt pin')
 
 class GicV2(BaseGic):
     type = 'GicV2'
     cxx_header = "dev/arm/gic_v2.hh"
+    cxx_class = 'gem5::GicV2'
 
     dist_addr = Param.Addr("Address for distributor")
     cpu_addr = Param.Addr("Address for cpu")
@@ -174,6 +176,7 @@ class Gic400(GicV2):
 class Gicv2mFrame(SimObject):
     type = 'Gicv2mFrame'
     cxx_header = "dev/arm/gic_v2m.hh"
+    cxx_class = 'gem5::Gicv2mFrame'
     spi_base = Param.UInt32(0x0, "Frame SPI base number");
     spi_len = Param.UInt32(0x0, "Frame SPI total number");
     addr = Param.Addr("Address for frame PIO")
@@ -181,6 +184,7 @@ class Gicv2mFrame(SimObject):
 class Gicv2m(PioDevice):
     type = 'Gicv2m'
     cxx_header = "dev/arm/gic_v2m.hh"
+    cxx_class = 'gem5::Gicv2m'
 
     pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
     gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
@@ -189,6 +193,7 @@ class Gicv2m(PioDevice):
 class VGic(PioDevice):
     type = 'VGic'
     cxx_header = "dev/arm/vgic.hh"
+    cxx_class = 'gem5::VGic'
     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     platform = Param.Platform(Parent.any, "Platform this device is part of.")
     vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
@@ -232,6 +237,7 @@ class VGic(PioDevice):
 class Gicv3Its(BasicPioDevice):
     type = 'Gicv3Its'
     cxx_header = "dev/arm/gic_v3_its.hh"
+    cxx_class = 'gem5::Gicv3Its'
 
     dma = RequestPort("DMA port")
     pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size")
@@ -253,6 +259,7 @@ class Gicv3Its(BasicPioDevice):
 class Gicv3(BaseGic):
     type = 'Gicv3'
     cxx_header = "dev/arm/gic_v3.hh"
+    cxx_class = 'gem5::Gicv3'
 
     # Used for DTB autogeneration
     _state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)

src/dev/arm/NoMali.py

@@ -47,6 +47,7 @@ class NoMaliGpuType(Enum): vals = [
 class NoMaliGpu(PioDevice):
     type = 'NoMaliGpu'
     cxx_header = "dev/arm/gpu_nomali.hh"
+    cxx_class = 'gem5::NoMaliGpu'
 
     pio_addr = Param.Addr("Device base address")
 
@@ -69,6 +70,7 @@ class CustomNoMaliGpu(NoMaliGpu):
 
     type = 'CustomNoMaliGpu'
     cxx_header = "dev/arm/gpu_nomali.hh"
+    cxx_class = 'gem5::CustomNoMaliGpu'
 
     gpu_id = Param.UInt32("")
     l2_features = Param.UInt32("")

src/dev/arm/RealView.py

@@ -84,12 +84,14 @@ class AmbaPioDevice(BasicPioDevice):
     type = 'AmbaPioDevice'
     abstract = True
     cxx_header = "dev/arm/amba_device.hh"
+    cxx_class = 'gem5::AmbaPioDevice'
     amba_id = Param.UInt32("ID of AMBA device for kernel detection")
 
 class AmbaIntDevice(AmbaPioDevice):
     type = 'AmbaIntDevice'
     abstract = True
     cxx_header = "dev/arm/amba_device.hh"
+    cxx_class = 'gem5::AmbaIntDevice'
     interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
     int_delay = Param.Latency("100ns",
             "Time between action and interrupt generation by device")
@@ -98,6 +100,7 @@ class AmbaDmaDevice(DmaDevice):
     type = 'AmbaDmaDevice'
     abstract = True
     cxx_header = "dev/arm/amba_device.hh"
+    cxx_class = 'gem5::AmbaDmaDevice'
     pio_addr = Param.Addr("Address for AMBA responder interface")
     pio_latency = Param.Latency("10ns", "Time between action and write/read"
                                         "result by AMBA DMA Device")
@@ -107,6 +110,7 @@ class AmbaDmaDevice(DmaDevice):
 class A9SCU(BasicPioDevice):
     type = 'A9SCU'
     cxx_header = "dev/arm/a9scu.hh"
+    cxx_class = 'gem5::A9SCU'
 
 class ArmPciIntRouting(Enum): vals = [
     'ARM_PCI_INT_STATIC',
@@ -117,6 +121,7 @@ class ArmPciIntRouting(Enum): vals = [
 class GenericArmPciHost(GenericPciHost):
     type = 'GenericArmPciHost'
     cxx_header = "dev/arm/pci_host.hh"
+    cxx_class = 'gem5::GenericArmPciHost'
 
     int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
     int_base = Param.Unsigned("PCI interrupt base")
@@ -208,6 +213,7 @@ class GenericArmPciHost(GenericPciHost):
 class RealViewCtrl(BasicPioDevice):
     type = 'RealViewCtrl'
     cxx_header = "dev/arm/rv_ctrl.hh"
+    cxx_class = 'gem5::RealViewCtrl'
     proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
     proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
     idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
@@ -227,6 +233,7 @@ class RealViewCtrl(BasicPioDevice):
 class RealViewOsc(ClockDomain):
     type = 'RealViewOsc'
     cxx_header = "dev/arm/rv_ctrl.hh"
+    cxx_class = 'gem5::RealViewOsc'
 
     parent = Param.RealViewCtrl(Parent.any, "RealView controller")
 
@@ -275,6 +282,7 @@ class RealViewOsc(ClockDomain):
 class RealViewTemperatureSensor(SimObject):
     type = 'RealViewTemperatureSensor'
     cxx_header = "dev/arm/rv_ctrl.hh"
+    cxx_class = 'gem5::RealViewTemperatureSensor'
 
     parent = Param.RealViewCtrl(Parent.any, "RealView controller")
 
@@ -362,7 +370,9 @@ ARM DUI 0604E for details.
 class AmbaFake(AmbaPioDevice):
     type = 'AmbaFake'
     cxx_header = "dev/arm/amba_fake.hh"
-    ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
+    cxx_class = 'gem5::AmbaFake'
+    ignore_access = Param.Bool(False,
+        "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
     amba_id = 0;
 
 # Simple fixed-rate clock source. Intended to be instantiated in Platform
@@ -388,9 +398,12 @@ class FixedClock(SrcClockDomain):
 class Pl011(Uart):
     type = 'Pl011'
     cxx_header = "dev/arm/pl011.hh"
+    cxx_class = 'gem5::Pl011'
     interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
-    end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
-    int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
+    end_on_eot = Param.Bool(False,
+        "End the simulation when a EOT is received on the UART")
+    int_delay = Param.Latency("100ns",
+        "Time between action and interrupt generation by UART")
 
     def generateDeviceTree(self, state):
         node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
@@ -409,6 +422,7 @@ class Pl011(Uart):
 class Sp804(AmbaPioDevice):
     type = 'Sp804'
     cxx_header = "dev/arm/timer_sp804.hh"
+    cxx_class = 'gem5::Sp804'
     int0 = Param.ArmSPI("Interrupt that connects to GIC")
     clock0 = Param.Clock('1MHz', "Clock speed of the input")
     int1 = Param.ArmSPI("Interrupt that connects to GIC")
@@ -425,6 +439,7 @@ Reference:
 
     type = 'Sp805'
     cxx_header = 'dev/arm/watchdog_sp805.hh'
+    cxx_class = 'gem5::Sp805'
 
     amba_id = 0x00141805
 
@@ -446,6 +461,7 @@ Reference:
 class GenericWatchdog(PioDevice):
     type = 'GenericWatchdog'
     cxx_header = 'dev/arm/watchdog_generic.hh'
+    cxx_class = 'gem5::GenericWatchdog'
 
     refresh_start = Param.Addr("Start address for the refresh frame")
     control_start = Param.Addr("Start address for the control frame")
@@ -461,13 +477,16 @@ class GenericWatchdog(PioDevice):
 class CpuLocalTimer(BasicPioDevice):
     type = 'CpuLocalTimer'
     cxx_header = "dev/arm/timer_cpulocal.hh"
+    cxx_class = 'gem5::CpuLocalTimer'
     int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC")
     int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC")
 
 class PL031(AmbaIntDevice):
     type = 'PL031'
     cxx_header = "dev/arm/rtc_pl031.hh"
-    time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
+    cxx_class = 'gem5::PL031'
+    time = Param.Time('01/01/2009',
+        "System time to use ('Now' for actual time)")
     amba_id = 0x00041031
 
     def generateDeviceTree(self, state):
@@ -484,6 +503,7 @@ class PL031(AmbaIntDevice):
 class Pl050(AmbaIntDevice):
     type = 'Pl050'
     cxx_header = "dev/arm/kmi.hh"
+    cxx_class = 'gem5::Pl050'
     amba_id = 0x00141050
 
     ps2 = Param.PS2Device("PS/2 device")
@@ -501,14 +521,18 @@ class Pl050(AmbaIntDevice):
 class Pl111(AmbaDmaDevice):
     type = 'Pl111'
     cxx_header = "dev/arm/pl111.hh"
+    cxx_class = 'gem5::Pl111'
     pixel_clock = Param.Clock('24MHz', "Pixel clock")
-    vnc   = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
+    vnc   = Param.VncInput(Parent.any,
+        "Vnc server for remote frame buffer display")
     amba_id = 0x00141111
-    enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
+    enable_capture = Param.Bool(True,
+        "capture frame to system.framebuffer.bmp")
 
 class HDLcd(AmbaDmaDevice):
     type = 'HDLcd'
     cxx_header = "dev/arm/hdlcd.hh"
+    cxx_class = 'gem5::HDLcd'
     vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
                                      "display")
     amba_id = 0x00141000
@@ -630,6 +654,7 @@ Reference:
 
     type = 'FVPBasePwrCtrl'
     cxx_header = 'dev/arm/fvp_base_pwr_ctrl.hh'
+    cxx_class = 'gem5::FVPBasePwrCtrl'
 
 class GenericMHU(MHU):
     lowp_scp2ap = Scp2ApDoorbell(
@@ -651,6 +676,7 @@ class GenericMHU(MHU):
 class RealView(Platform):
     type = 'RealView'
     cxx_header = "dev/arm/realview.hh"
+    cxx_class = 'gem5::RealView'
     _mem_regions = [ AddrRange(0, size='256MiB') ]
     _num_pci_dev = 0
 

src/dev/arm/SMMUv3.py

@@ -42,6 +42,7 @@ from m5.objects.ClockedObject import ClockedObject
 class SMMUv3DeviceInterface(ClockedObject):
     type = 'SMMUv3DeviceInterface'
     cxx_header = 'dev/arm/smmu_v3_deviceifc.hh'
+    cxx_class = 'gem5::SMMUv3DeviceInterface'
 
     device_port = ResponsePort('Device port')
     slave     = DeprecatedParam(device_port,
@@ -81,6 +82,7 @@ class SMMUv3DeviceInterface(ClockedObject):
 class SMMUv3(ClockedObject):
     type = 'SMMUv3'
     cxx_header = 'dev/arm/smmu_v3.hh'
+    cxx_class = 'gem5::SMMUv3'
 
     request = RequestPort('Request port')
     walker = RequestPort(

src/dev/arm/UFSHostDevice.py

@@ -42,6 +42,7 @@ from m5.objects.AbstractNVM import *
 class UFSHostDevice(DmaDevice):
     type = 'UFSHostDevice'
     cxx_header = "dev/arm/ufs_device.hh"
+    cxx_class = 'gem5::UFSHostDevice'
     pio_addr = Param.Addr("Address for SCSI configuration responder interface")
     pio_latency = Param.Latency("10ns", "Time between action and write/read \
        result by AMBA DMA Device")

src/dev/arm/VirtIOMMIO.py

@@ -46,6 +46,7 @@ from m5.objects.VirtIO import VirtIODeviceBase, VirtIODummyDevice
 class MmioVirtIO(BasicPioDevice):
     type = 'MmioVirtIO'
     cxx_header = 'dev/arm/vio_mmio.hh'
+    cxx_class = 'gem5::MmioVirtIO'
 
     pio_size = Param.Addr(4096, "IO range")
     interrupt = Param.ArmInterruptPin("Interrupt to use for this device")

src/dev/arm/a9scu.cc

@@ -43,6 +43,9 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
+namespace gem5
+{
+
 A9SCU::A9SCU(const Params &p)
     : BasicPioDevice(p, 0x60)
 {
@@ -103,3 +106,5 @@ A9SCU::write(PacketPtr pkt)
     pkt->makeAtomicResponse();
     return pioDelay;
 }
+
+} // namespace gem5

src/dev/arm/a9scu.hh

@@ -45,6 +45,9 @@
  * This defines the snoop control unit register on an A9
  */
 
+namespace gem5
+{
+
 class A9SCU : public BasicPioDevice
 {
   protected:
@@ -78,6 +81,7 @@ class A9SCU : public BasicPioDevice
     virtual Tick write(PacketPtr pkt);
 };
 
+} // namespace gem5
 
 #endif // __DEV_ARM_A9SCU_HH__
 

src/dev/arm/abstract_nvm.hh

@@ -42,6 +42,9 @@
 #include "params/AbstractNVM.hh"
 #include "sim/sim_object.hh"
 
+namespace gem5
+{
+
 /**
  * This is an interface between the disk interface (which will handle the disk
  * data transactions) and the timing model. The timing model only takes care
@@ -104,4 +107,6 @@ class AbstractNVM : public SimObject
                              const std::function<void()> &event) = 0;
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_ABSTRACT_NVM_HH__

src/dev/arm/amba.hh

@@ -40,6 +40,9 @@
 
 #include "mem/packet.hh"
 
+namespace gem5
+{
+
 namespace AMBA
 {
 
@@ -52,5 +55,6 @@ orderId(PacketPtr pkt)
 }
 
 } // namespace AMBA
+} // namespace gem5
 
 #endif // __DEV_ARM_AMBA_HH__

src/dev/arm/amba_device.cc

@@ -46,6 +46,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 const uint64_t AmbaVendor = 0xb105f00d00000000ULL;
 
 AmbaPioDevice::AmbaPioDevice(const Params &p, Addr pio_size)
@@ -84,3 +87,5 @@ AmbaDevice::readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
     pkt->setUintX((amba_id >> byte) & 0xFF, ByteOrder::little);
     return true;
 }
+
+} // namespace gem5

src/dev/arm/amba_device.hh

@@ -56,6 +56,8 @@
 #include "params/AmbaDmaDevice.hh"
 #include "params/AmbaIntDevice.hh"
 
+namespace gem5
+{
 
 class AmbaDevice
 {
@@ -108,5 +110,6 @@ class AmbaDmaDevice : public DmaDevice, public AmbaDevice
     AmbaDmaDevice(const Params &p, Addr pio_size = 0);
 };
 
+} // namespace gem5
 
 #endif //__DEV_ARM_AMBA_DEVICE_HH__

src/dev/arm/amba_fake.cc

@@ -45,6 +45,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 AmbaFake::AmbaFake(const Params &p)
     : AmbaPioDevice(p, 0x1000)
 {
@@ -81,3 +84,5 @@ AmbaFake::write(PacketPtr pkt)
     pkt->makeAtomicResponse();
     return pioDelay;
 }
+
+} // namespace gem5

src/dev/arm/amba_fake.hh

@@ -52,6 +52,9 @@
 #include "dev/arm/amba_device.hh"
 #include "params/AmbaFake.hh"
 
+namespace gem5
+{
+
 class AmbaFake : public AmbaPioDevice
 {
   public:
@@ -63,4 +66,6 @@ class AmbaFake : public AmbaPioDevice
 
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_AMBA_FAKE_H__

src/dev/arm/base_gic.cc

@@ -45,6 +45,9 @@
 #include "params/ArmSPI.hh"
 #include "params/BaseGic.hh"
 
+namespace gem5
+{
+
 BaseGic::BaseGic(const Params &p)
         : PioDevice(p),
           platform(p.platform)
@@ -243,3 +246,5 @@ ArmSigInterruptPin::clear()
         if (pin)
             pin->lower();
 }
+
+} // namespace gem5

src/dev/arm/base_gic.hh

@@ -52,6 +52,9 @@
 
 #include "enums/ArmInterruptType.hh"
 
+namespace gem5
+{
+
 class Platform;
 class RealView;
 class ThreadContext;
@@ -288,4 +291,6 @@ class ArmSigInterruptPin : public ArmInterruptPin
     void clear() override;
 };
 
-#endif
+} // namespace gem5
+
+#endif // __DEV_ARM_BASE_GIC_H__

src/dev/arm/css/MHU.py

@@ -43,21 +43,25 @@ class MhuDoorbell(Doorbell):
     type = 'MhuDoorbell'
     abstract = True
     cxx_header = "dev/arm/css/mhu.hh"
+    cxx_class = 'gem5::MhuDoorbell'
 
 class Scp2ApDoorbell(MhuDoorbell):
     type = 'Scp2ApDoorbell'
     cxx_header = "dev/arm/css/mhu.hh"
+    cxx_class = 'gem5::Scp2ApDoorbell'
 
     interrupt = Param.ArmInterruptPin("Interrupt Pin")
 
 class Ap2ScpDoorbell(MhuDoorbell):
     type = 'Ap2ScpDoorbell'
     cxx_header = "dev/arm/css/mhu.hh"
+    cxx_class = 'gem5::Ap2ScpDoorbell'
 
 # Message Handling Unit
 class MHU(BasicPioDevice):
     type = 'MHU'
     cxx_header = "dev/arm/css/mhu.hh"
+    cxx_class = 'gem5::MHU'
     pio_size = Param.Unsigned(0x1000, "MHU pio size")
 
     lowp_scp2ap = Param.Scp2ApDoorbell(

src/dev/arm/css/Scmi.py

@@ -46,7 +46,7 @@ class ScmiChannel(SimObject):
     """
     type = 'ScmiChannel'
     cxx_header = "dev/arm/css/scmi_platform.hh"
-    cxx_class = "scmi::VirtualChannel"
+    cxx_class = "gem5::scmi::VirtualChannel"
     shmem_range = Param.AddrRange(
         "Virtual channel's shared memory address range")
     phys_id = Param.Unsigned(4,
@@ -78,7 +78,7 @@ class ScmiAgentChannel(ScmiChannel):
     """
     type = 'ScmiAgentChannel'
     cxx_header = "dev/arm/css/scmi_platform.hh"
-    cxx_class = "scmi::AgentChannel"
+    cxx_class = "gem5::scmi::AgentChannel"
 
 
 class ScmiPlatformChannel(ScmiChannel):
@@ -87,7 +87,7 @@ class ScmiPlatformChannel(ScmiChannel):
     """
     type = 'ScmiPlatformChannel'
     cxx_header = "dev/arm/css/scmi_platform.hh"
-    cxx_class = "scmi::PlatformChannel"
+    cxx_class = "gem5::scmi::PlatformChannel"
 
 class ScmiCommunication(SimObject):
     """
@@ -98,7 +98,7 @@ class ScmiCommunication(SimObject):
     """
     type = 'ScmiCommunication'
     cxx_header = "dev/arm/css/scmi_platform.hh"
-    cxx_class = "scmi::Communication"
+    cxx_class = "gem5::scmi::Communication"
 
     agent_channel = Param.ScmiAgentChannel(
         "Agent to Platform channel")
@@ -108,7 +108,7 @@ class ScmiCommunication(SimObject):
 class ScmiPlatform(Scp):
     type = 'ScmiPlatform'
     cxx_header = "dev/arm/css/scmi_platform.hh"
-    cxx_class = "scmi::Platform"
+    cxx_class = "gem5::scmi::Platform"
 
     comms = VectorParam.ScmiCommunication([],
         "SCMI Communications")

src/dev/arm/css/Scp.py

@@ -40,3 +40,4 @@ class Scp(ClockedObject):
     type = 'Scp'
     abstract = True
     cxx_header = "dev/arm/css/scp.hh"
+    cxx_class = 'gem5::Scp'

src/dev/arm/css/mhu.cc

@@ -45,6 +45,9 @@
 #include "params/MHU.hh"
 #include "params/Scp2ApDoorbell.hh"
 
+namespace gem5
+{
+
 Scp2ApDoorbell::Scp2ApDoorbell(const Scp2ApDoorbellParams &p)
   : MhuDoorbell(p), interrupt(p.interrupt->get())
 {}
@@ -239,3 +242,5 @@ Ap2ScpDoorbell::clearInterrupt()
 {
     scp->clearInterrupt(this);
 }
+
+} // namespace gem5

src/dev/arm/css/mhu.hh

@@ -41,6 +41,9 @@
 #include "dev/arm/doorbell.hh"
 #include "dev/io_device.hh"
 
+namespace gem5
+{
+
 struct Ap2ScpDoorbellParams;
 class ArmInterruptPin;
 class MHU;
@@ -166,4 +169,6 @@ class MHU : public BasicPioDevice
     uint32_t scfg;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_CSS_MHU_H__

src/dev/arm/css/scmi_platform.cc

@@ -43,6 +43,9 @@
 #include "dev/arm/doorbell.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 using namespace scmi;
 
 AgentChannel::AgentChannel(const ScmiChannelParams &p)
@@ -303,3 +306,5 @@ Platform::find(AgentChannel* agent) const
 
     return nullptr;
 }
+
+} // namespace gem5

src/dev/arm/css/scmi_platform.hh

@@ -43,6 +43,9 @@
 #include "dev/dma_device.hh"
 #include "params/ScmiPlatform.hh"
 
+namespace gem5
+{
+
 class Doorbell;
 
 GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
@@ -327,5 +330,6 @@ class Platform : public Scp
 };
 
 } // namespace scmi
+} // namespace gem5
 
 #endif // __DEV_ARM_CSS_SCMI_PLATFORM_H__

src/dev/arm/css/scmi_protocols.cc

@@ -40,6 +40,9 @@
 #include "debug/SCMI.hh"
 #include "dev/arm/css/scmi_platform.hh"
 
+namespace gem5
+{
+
 using namespace scmi;
 
 const std::string
@@ -280,3 +283,5 @@ BaseProtocol::invalidCommand(Message &msg)
     payload.status = NOT_FOUND;
     msg.length = sizeof(uint32_t) * 2;
 }
+
+} // namespace gem5

src/dev/arm/css/scmi_protocols.hh

@@ -43,6 +43,9 @@
 
 #include "base/compiler.hh"
 
+namespace gem5
+{
+
 GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
 namespace scmi
 {
@@ -151,6 +154,7 @@ class BaseProtocol : public Protocol
 
 };
 
-}; // namespace scmi
+} // namespace scmi
+} // namespace gem5
 
 #endif

src/dev/arm/css/scp.hh

@@ -40,6 +40,9 @@
 
 #include "sim/clocked_object.hh"
 
+namespace gem5
+{
+
 class Doorbell;
 
 class Scp : public ClockedObject
@@ -55,4 +58,6 @@ class Scp : public ClockedObject
     virtual void clearInterrupt(const Doorbell *doorbell) = 0;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_CSS_SCP_H__

src/dev/arm/display.cc

@@ -39,6 +39,11 @@
 
 #include "params/Display.hh"
 
+namespace gem5
+{
+
 Display::Display(const DisplayParams &p)
   : SimObject(p)
 {}
+
+} // namespace gem5

src/dev/arm/display.hh

@@ -40,6 +40,9 @@
 
 #include "sim/sim_object.hh"
 
+namespace gem5
+{
+
 struct DisplayParams;
 
 class Display : public SimObject
@@ -48,4 +51,6 @@ class Display : public SimObject
     Display(const DisplayParams &p);
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_DISPLAY_H__

src/dev/arm/doorbell.hh

@@ -41,6 +41,9 @@
 #include "params/Doorbell.hh"
 #include "sim/sim_object.hh"
 
+namespace gem5
+{
+
 /**
  * Generic doorbell interface.
  * A Doorbell implementation will override the set and
@@ -63,4 +66,6 @@ class Doorbell : public SimObject
     const Addr _clearAddress;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_DOORBELL_H__

src/dev/arm/energy_ctrl.cc

@@ -45,6 +45,9 @@
 #include "sim/dvfs_handler.hh"
 #include "sim/serialize.hh"
 
+namespace gem5
+{
+
 EnergyCtrl::EnergyCtrl(const Params &p)
     : BasicPioDevice(p, PIO_NUM_FIELDS * 4),        // each field is 32 bit
       dvfsHandler(p.dvfs_handler),
@@ -255,3 +258,5 @@ EnergyCtrl::init()
 {
     BasicPioDevice::init();
 }
+
+} // namespace gem5

src/dev/arm/energy_ctrl.hh

@@ -56,6 +56,9 @@
 #include "dev/io_device.hh"
 #include "params/EnergyCtrl.hh"
 
+namespace gem5
+{
+
 class DVFSHandler;
 
 class EnergyCtrl : public BasicPioDevice
@@ -181,4 +184,7 @@ class EnergyCtrl : public BasicPioDevice
 
     EventFunctionWrapper updateAckEvent;
 };
+
+} // namespace gem5
+
 #endif //__DEV_ARM_ENERGY_CTRL_HH__

src/dev/arm/flash_device.cc

@@ -55,6 +55,9 @@
 #include "base/trace.hh"
 #include "debug/Drain.hh"
 
+namespace gem5
+{
+
 /**
  * Flash Device constructor and destructor
  */
@@ -576,3 +579,5 @@ FlashDevice::checkDrain()
         signalDrainDone();
     }
 }
+
+} // namespace gem5

src/dev/arm/flash_device.hh

@@ -46,6 +46,9 @@
 #include "params/FlashDevice.hh"
 #include "sim/serialize.hh"
 
+namespace gem5
+{
+
 /**
  * Flash Device model
  * The Flash Device model is a timing model for a NAND flash device.
@@ -198,4 +201,7 @@ class FlashDevice : public AbstractNVM
     /** Completion event */
     EventFunctionWrapper planeEvent;
 };
+
+} // namespace gem5
+
 #endif //__DEV_ARM_FLASH_DEVICE_HH__

src/dev/arm/fvp_base_pwr_ctrl.cc

@@ -47,6 +47,9 @@
 #include "params/FVPBasePwrCtrl.hh"
 #include "sim/system.hh"
 
+namespace gem5
+{
+
 FVPBasePwrCtrl::FVPBasePwrCtrl(const FVPBasePwrCtrlParams &params)
     : BasicPioDevice(params, 0x1000),
       regs(),
@@ -310,3 +313,5 @@ FVPBasePwrCtrl::startCoreUp(ThreadContext *const tc)
     ArmISA::Reset().invoke(tc);
     tc->activate();
 }
+
+} // namespace gem5

src/dev/arm/fvp_base_pwr_ctrl.hh

@@ -43,6 +43,9 @@
 #include "base/bitunion.hh"
 #include "dev/io_device.hh"
 
+namespace gem5
+{
+
 class ArmSystem;
 struct FVPBasePwrCtrlParams;
 class ThreadContext;
@@ -182,4 +185,6 @@ class FVPBasePwrCtrl : public BasicPioDevice
     ArmSystem &system;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_FVP_BASE_PWR_CTRL_HH__

src/dev/arm/generic_timer.cc

@@ -52,6 +52,9 @@
 #include "params/GenericTimerMem.hh"
 #include "params/SystemCounter.hh"
 
+namespace gem5
+{
+
 using namespace ArmISA;
 
 SystemCounter::SystemCounter(const SystemCounterParams &p)
@@ -1580,3 +1583,5 @@ GenericTimerMem::timerCtrlWrite(Addr addr, size_t size, uint64_t data,
              "(0x%x:%i), assuming WI\n", addr, size);
     }
 }
+
+} // namespace gem5

src/dev/arm/generic_timer.hh

@@ -63,6 +63,9 @@
 ///     G6.2  - The AArch32 view of the Generic Timer
 ///     I2 - System Level Implementation of the Generic Timer
 
+namespace gem5
+{
+
 class Checkpoint;
 struct SystemCounterParams;
 struct GenericTimerParams;
@@ -585,4 +588,6 @@ class GenericTimerMem : public PioDevice
     ArmSystem &system;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_GENERIC_TIMER_HH__

src/dev/arm/generic_timer_miscregs_types.hh

@@ -40,6 +40,9 @@
 
 #include "base/bitunion.hh"
 
+namespace gem5
+{
+
 namespace ArmISA
 {
     BitUnion64(CNTKCTL)
@@ -93,4 +96,6 @@ namespace ArmISA
     // ENDIF Armv8.1-VHE && HCR_EL2.E2H == 1
 }
 
+} // namespace gem5
+
 #endif // __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__

src/dev/arm/gic_v2.cc

@@ -50,6 +50,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 const AddrRange GicV2::GICD_IGROUPR   (0x080, 0x100);
 const AddrRange GicV2::GICD_ISENABLER (0x100, 0x180);
 const AddrRange GicV2::GICD_ICENABLER (0x180, 0x200);
@@ -1095,3 +1098,5 @@ GicV2::BankedRegs::unserialize(CheckpointIn &cp)
     UNSERIALIZE_ARRAY(intConfig, 2);
     UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
 }
+
+} // namespace gem5

src/dev/arm/gic_v2.hh

@@ -56,6 +56,9 @@
 #include "dev/platform.hh"
 #include "params/GicV2.hh"
 
+namespace gem5
+{
+
 class GicV2 : public BaseGic, public BaseGicRegisters
 {
   protected:
@@ -547,4 +550,6 @@ class GicV2 : public BaseGic, public BaseGicRegisters
     void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_GIC_H__

src/dev/arm/gic_v2m.cc

@@ -64,6 +64,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 Gicv2m::Gicv2m(const Params &p)
     : PioDevice(p), pioDelay(p.pio_delay), frames(p.frames), gic(p.gic)
 {
@@ -154,3 +157,5 @@ Gicv2m::frameFromAddr(Addr a) const
     }
     return -1;
 }
+
+} // namespace gem5

src/dev/arm/gic_v2m.hh

@@ -51,6 +51,9 @@
 #include "params/Gicv2m.hh"
 #include "params/Gicv2mFrame.hh"
 
+namespace gem5
+{
+
 /**
  * Ultimately this class should be embedded in the Gicv2m class, but
  * this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame'
@@ -115,4 +118,6 @@ class Gicv2m : public PioDevice
     int frameFromAddr(Addr a) const;
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_GIC_V2M_H__

src/dev/arm/gic_v3.cc

@@ -51,6 +51,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 Gicv3::Gicv3(const Params &p)
     : BaseGic(p)
 {
@@ -298,3 +301,5 @@ Gicv3::unserialize(CheckpointIn & cp)
         cpuInterfaces[cpu_interface_id]->unserializeSection(cp,
             csprintf("cpuInterface.%i", cpu_interface_id));
 }
+
+} // namespace gem5

src/dev/arm/gic_v3.hh

@@ -45,6 +45,9 @@
 #include "dev/arm/base_gic.hh"
 #include "params/Gicv3.hh"
 
+namespace gem5
+{
+
 class Gicv3CPUInterface;
 class Gicv3Distributor;
 class Gicv3Redistributor;
@@ -161,4 +164,6 @@ class Gicv3 : public BaseGic
     void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_GICV3_H__

src/dev/arm/gic_v3_cpu_interface.cc

@@ -47,6 +47,9 @@
 #include "dev/arm/gic_v3_distributor.hh"
 #include "dev/arm/gic_v3_redistributor.hh"
 
+namespace gem5
+{
+
 using namespace ArmISA;
 
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
@@ -2336,7 +2339,7 @@ Gicv3CPUInterface::inSecureState() const
 
     CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
     SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
-    return ::inSecureState(scr, cpsr);
+    return gem5::inSecureState(scr, cpsr);
 }
 
 int
@@ -2623,3 +2626,5 @@ Gicv3CPUInterface::unserialize(CheckpointIn & cp)
     UNSERIALIZE_SCALAR(hppi.prio);
     UNSERIALIZE_ENUM(hppi.group);
 }
+
+} // namespace gem5

src/dev/arm/gic_v3_cpu_interface.hh

@@ -44,6 +44,9 @@
 #include "arch/arm/isa_device.hh"
 #include "dev/arm/gic_v3.hh"
 
+namespace gem5
+{
+
 class Gicv3Distributor;
 class Gicv3Redistributor;
 
@@ -357,4 +360,6 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     void setThreadContext(ThreadContext *tc) override;
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__

src/dev/arm/gic_v3_distributor.cc

@@ -49,6 +49,9 @@
 #include "dev/arm/gic_v3_cpu_interface.hh"
 #include "dev/arm/gic_v3_redistributor.hh"
 
+namespace gem5
+{
+
 const AddrRange Gicv3Distributor::GICD_IGROUPR   (0x0080, 0x0100);
 const AddrRange Gicv3Distributor::GICD_ISENABLER (0x0100, 0x0180);
 const AddrRange Gicv3Distributor::GICD_ICENABLER (0x0180, 0x0200);
@@ -1213,3 +1216,5 @@ Gicv3Distributor::unserialize(CheckpointIn & cp)
     UNSERIALIZE_CONTAINER(irqNsacr);
     UNSERIALIZE_CONTAINER(irqAffinityRouting);
 }
+
+} // namespace gem5

src/dev/arm/gic_v3_distributor.hh

@@ -45,6 +45,9 @@
 #include "dev/arm/gic_v3.hh"
 #include "sim/serialize.hh"
 
+namespace gem5
+{
+
 class Gicv3Distributor : public Serializable
 {
   private:
@@ -271,4 +274,6 @@ class Gicv3Distributor : public Serializable
                bool is_secure_access);
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__

src/dev/arm/gic_v3_its.cc

@@ -53,6 +53,9 @@
 
 #define COMMAND(x, method) { x, DispatchEntry(#x, method) }
 
+namespace gem5
+{
+
 const AddrRange Gicv3Its::GITS_BASER(0x0100, 0x0140);
 
 const uint32_t Gicv3Its::CTLR_QUIESCENT = 0x80000000;
@@ -1291,3 +1294,5 @@ Gicv3Its::moveAllPendingState(
 
     rd2->updateDistributor();
 }
+
+} // namespace gem5

src/dev/arm/gic_v3_its.hh

@@ -50,6 +50,9 @@
 #include "dev/dma_device.hh"
 #include "params/Gicv3Its.hh"
 
+namespace gem5
+{
+
 class Gicv3;
 class Gicv3Redistributor;
 class ItsProcess;
@@ -79,9 +82,10 @@ struct ItsAction
  */
 class Gicv3Its : public BasicPioDevice
 {
-    friend class ::ItsProcess;
-    friend class ::ItsTranslation;
-    friend class ::ItsCommand;
+    friend class gem5::ItsProcess;
+    friend class gem5::ItsTranslation;
+    friend class gem5::ItsCommand;
+
   public:
     class DataPort : public RequestPort
     {
@@ -542,4 +546,6 @@ class ItsCommand : public ItsProcess
     }
 };
 
+} // namespace gem5
+
 #endif

src/dev/arm/gic_v3_redistributor.cc

@@ -46,6 +46,9 @@
 #include "dev/arm/gic_v3_cpu_interface.hh"
 #include "dev/arm/gic_v3_distributor.hh"
 
+namespace gem5
+{
+
 using namespace ArmISA;
 
 const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
@@ -1093,3 +1096,5 @@ Gicv3Redistributor::unserialize(CheckpointIn & cp)
     UNSERIALIZE_SCALAR(lpiIDBits);
     UNSERIALIZE_SCALAR(lpiPendingTablePtr);
 }
+
+} // namespace gem5

src/dev/arm/gic_v3_redistributor.hh

@@ -45,6 +45,9 @@
 #include "dev/arm/gic_v3.hh"
 #include "sim/serialize.hh"
 
+namespace gem5
+{
+
 class Gicv3CPUInterface;
 class Gicv3Distributor;
 class Gicv3Its;
@@ -259,4 +262,6 @@ class Gicv3Redistributor : public Serializable
     void write(Addr addr, uint64_t data, size_t size, bool is_secure_access);
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__

src/dev/arm/gpu_nomali.cc

@@ -46,6 +46,9 @@
 #include "params/CustomNoMaliGpu.hh"
 #include "params/NoMaliGpu.hh"
 
+namespace gem5
+{
+
 static const std::map<enums::NoMaliGpuType, nomali_gpu_type_t> gpuTypeMap{
     { enums::T60x, NOMALI_GPU_T60X },
     { enums::T62x, NOMALI_GPU_T62X },
@@ -374,3 +377,5 @@ CustomNoMaliGpu::onReset()
     for (const auto &reg : idRegs)
         writeRegRaw(reg.first, reg.second);
 }
+
+} // namespace gem5

src/dev/arm/gpu_nomali.hh

@@ -43,6 +43,9 @@
 #include "dev/io_device.hh"
 #include "libnomali/nomali.h"
 
+namespace gem5
+{
+
 struct NoMaliGpuParams;
 struct CustomNoMaliGpuParams;
 class RealView;
@@ -199,4 +202,6 @@ class CustomNoMaliGpu : public NoMaliGpu
     std::map<nomali_addr_t, uint32_t> idRegs;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_NOMALI_GPU_HH__

src/dev/arm/hdlcd.cc

@@ -53,6 +53,8 @@
 
 using std::vector;
 
+namespace gem5
+{
 
 // initialize hdlcd registers
 HDLcd::HDLcd(const HDLcdParams &p)
@@ -688,3 +690,5 @@ HDLcd::PixelPump::dumpSettings()
     inform("PixelPump vertical fron porch: %u", t.vFrontPorch);
     inform("PixelPump vertical fron porch: %u", t.vSync);
 }
+
+} // namespace gem5

src/dev/arm/hdlcd.hh

@@ -84,6 +84,9 @@
 #include "dev/pixelpump.hh"
 #include "sim/serialize.hh"
 
+namespace gem5
+{
+
 class VncInput;
 struct HDLcdParams;
 class HDLcdPixelPump;
@@ -418,4 +421,6 @@ class HDLcd: public AmbaDmaDevice
     } stats;
 };
 
+} // namespace gem5
+
 #endif

src/dev/arm/kmi.cc

@@ -48,6 +48,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 Pl050::Pl050(const Pl050Params &p)
     : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
       rawInterrupts(0),
@@ -219,3 +222,5 @@ Pl050::unserialize(CheckpointIn &cp)
     UNSERIALIZE_SCALAR(clkdiv);
     paramIn(cp, "raw_ints", rawInterrupts);
 }
+
+} // namespace gem5

src/dev/arm/kmi.hh

@@ -52,6 +52,9 @@
 #include "dev/arm/amba_device.hh"
 #include "params/Pl050.hh"
 
+namespace gem5
+{
+
 namespace ps2 {
 class Device;
 } // namespace ps2
@@ -137,4 +140,6 @@ class Pl050 : public AmbaIntDevice
     void unserialize(CheckpointIn &cp) override;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_PL050_HH__

src/dev/arm/pci_host.cc

@@ -39,6 +39,9 @@
 
 #include "params/GenericArmPciHost.hh"
 
+namespace gem5
+{
+
 GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams &p)
     : GenericPciHost(p),
       intPolicy(p.int_policy), intBase(p.int_base),
@@ -68,3 +71,5 @@ GenericArmPciHost::mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const
         fatal("Unsupported PCI interrupt routing policy.");
     }
 }
+
+} // namespace gem5

src/dev/arm/pci_host.hh

@@ -41,6 +41,9 @@
 #include "dev/pci/host.hh"
 #include "enums/ArmPciIntRouting.hh"
 
+namespace gem5
+{
+
 class BaseGic;
 struct GenericArmPciHostParams;
 
@@ -61,4 +64,6 @@ class GenericArmPciHost
     const uint32_t intCount;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_PCI_HOST_HH__

src/dev/arm/pl011.cc

@@ -50,6 +50,9 @@
 #include "params/Pl011.hh"
 #include "sim/sim_exit.hh"
 
+namespace gem5
+{
+
 Pl011::Pl011(const Pl011Params &p)
     : Uart(p, 0x1000),
       intEvent([this]{ generateInterrupt(); }, name()),
@@ -296,3 +299,5 @@ Pl011::unserialize(CheckpointIn &cp)
     paramIn(cp, "imsc_serial", imsc);
     paramIn(cp, "rawInt_serial", rawInt);
 }
+
+} // namespace gem5

src/dev/arm/pl011.hh

@@ -49,6 +49,9 @@
 #include "dev/arm/amba_device.hh"
 #include "dev/serial/uart.hh"
 
+namespace gem5
+{
+
 class BaseGic;
 struct Pl011Params;
 
@@ -180,4 +183,6 @@ class Pl011 : public Uart, public AmbaDevice
     const Tick intDelay;
 };
 
+} // namespace gem5
+
 #endif //__DEV_ARM_PL011_H__

src/dev/arm/pl111.cc

@@ -52,6 +52,9 @@
 // we open up the entire namespace std
 using std::vector;
 
+namespace gem5
+{
+
 // initialize clcd registers
 Pl111::Pl111(const Params &p)
     : AmbaDmaDevice(p, 0x10000), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
@@ -740,3 +743,5 @@ Pl111::getAddrRanges() const
     ranges.push_back(RangeSize(pioAddr, pioSize));
     return ranges;
 }
+
+} // namespace gem5

src/dev/arm/pl111.hh

@@ -53,6 +53,9 @@
 #include "params/Pl111.hh"
 #include "sim/serialize.hh"
 
+namespace gem5
+{
+
 class VncInput;
 
 class Pl111: public AmbaDmaDevice
@@ -375,4 +378,6 @@ class Pl111: public AmbaDmaDevice
     AddrRangeList getAddrRanges() const override;
 };
 
+} // namespace gem5
+
 #endif

src/dev/arm/realview.cc

@@ -47,6 +47,9 @@
 #include "base/logging.hh"
 #include "dev/arm/base_gic.hh"
 
+namespace gem5
+{
+
 RealView::RealView(const Params &p)
     : Platform(p), gic(nullptr)
 {}
@@ -76,3 +79,5 @@ RealView::clearPciInt(int line)
 {
     gic->clearInt(line);
 }
+
+} // namespace gem5

src/dev/arm/realview.hh

@@ -50,6 +50,9 @@
 #include "dev/platform.hh"
 #include "params/RealView.hh"
 
+namespace gem5
+{
+
 class BaseGic;
 class IdeController;
 
@@ -74,4 +77,6 @@ class RealView : public Platform
     void clearPciInt(int line) override;
 };
 
+} // namespace gem5
+
 #endif // __DEV_ARM_RealView_HH__

src/dev/arm/rtc_pl031.cc

@@ -46,6 +46,9 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
+namespace gem5
+{
+
 PL031::PL031(const Params &p)
     : AmbaIntDevice(p, 0x1000), lastWrittenTick(0), loadVal(0), matchVal(0),
       rawInt(false), maskInt(false), pendingInt(false),
@@ -223,3 +226,5 @@ PL031::unserialize(CheckpointIn &cp)
         schedule(matchEvent, event_time);
     }
 }
+
+} // namespace gem5

src/dev/arm/rtc_pl031.hh

@@ -45,6 +45,9 @@
  * This implements the ARM Primecell 031 RTC
  */
 
+namespace gem5
+{
+
 class PL031 : public AmbaIntDevice
 {
   protected:
@@ -124,5 +127,6 @@ class PL031 : public AmbaIntDevice
     void unserialize(CheckpointIn &cp) override;
 };
 
+} // namespace gem5
 
 #endif // __DEV_ARM_RTC_PL031_HH__

src/dev/arm/rv_ctrl.cc

@@ -45,6 +45,9 @@
 #include "sim/system.hh"
 #include "sim/voltage_domain.hh"
 
+namespace gem5
+{
+
 RealViewCtrl::RealViewCtrl(const Params &p)
     : BasicPioDevice(p, 0xD4), flags(0), scData(0)
 {
@@ -313,3 +316,5 @@ RealViewTemperatureSensor::read() const
     // Report a dummy 25 degrees temperature
     return 25000000;
 }
+
+} // namespace gem5

src/dev/arm/rv_ctrl.hh

@@ -48,6 +48,9 @@
  * This implements the simple real view registers on a PBXA9
  */
 
+namespace gem5
+{
+
 class RealViewCtrl : public BasicPioDevice
 {
   public:
@@ -243,5 +246,6 @@ class RealViewTemperatureSensor
     System * system;
 };
 
+} // namespace gem5
 
 #endif // __DEV_ARM_RV_HH__

src/dev/arm/smmu_v3.cc

@@ -52,6 +52,9 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
+namespace gem5
+{
+
 SMMUv3::SMMUv3(const SMMUv3Params &params) :
     ClockedObject(params),
     system(*params.system),
@@ -818,3 +821,5 @@ SMMUv3::getPort(const std::string &name, PortID id)
         return ClockedObject::getPort(name, id);
     }
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3.hh

@@ -76,6 +76,10 @@
  * - Checkpointing is not supported
  * - Stall/resume for faulting transactions is not supported
  */
+
+namespace gem5
+{
+
 class SMMUTranslationProcess;
 
 class SMMUv3 : public ClockedObject
@@ -195,4 +199,6 @@ class SMMUv3 : public ClockedObject
                           PortID id = InvalidPortID) override;
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_HH__ */

src/dev/arm/smmu_v3_caches.cc

@@ -58,6 +58,9 @@
  * TODO: move more code into this base class to reduce duplication.
  */
 
+namespace gem5
+{
+
 SMMUv3BaseCache::SMMUv3BaseCache(const std::string &policy_name, uint32_t seed,
     statistics::Group *parent, const std::string &name)
   : replacementPolicy(decodePolicyName(policy_name)),
@@ -1330,3 +1333,5 @@ WalkCache::WalkCacheStats::~WalkCacheStats()
     for (auto avg_hitrate : averageHitRateByStageLevel)
         delete avg_hitrate;
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3_caches.hh

@@ -51,6 +51,9 @@
 
 #define WALK_CACHE_LEVELS 4
 
+namespace gem5
+{
+
 enum
 {
     SMMU_CACHE_REPL_ROUND_ROBIN,
@@ -358,4 +361,6 @@ class WalkCache : public SMMUv3BaseCache
                                  unsigned stage, unsigned level);
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_CACHES_HH__ */

src/dev/arm/smmu_v3_cmdexec.cc

@@ -40,6 +40,9 @@
 #include "base/bitfield.hh"
 #include "dev/arm/smmu_v3.hh"
 
+namespace gem5
+{
+
 void
 SMMUCommandExecProcess::main(Yield &yield)
 {
@@ -86,3 +89,5 @@ SMMUCommandExecProcess::main(Yield &yield)
         doSleep(yield);
     }
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3_cmdexec.hh

@@ -41,6 +41,9 @@
 #include "dev/arm/smmu_v3_defs.hh"
 #include "dev/arm/smmu_v3_proc.hh"
 
+namespace gem5
+{
+
 class SMMUv3;
 
 class SMMUCommandExecProcess : public SMMUProcess
@@ -65,4 +68,6 @@ class SMMUCommandExecProcess : public SMMUProcess
     bool isBusy() const { return busy; }
 };
 
+} // namespace gem5
+
 #endif  /* __DEV_ARM_SMMU_V3_CMDEXEC_HH__ */

src/dev/arm/smmu_v3_defs.hh

@@ -42,6 +42,9 @@
 
 #include "base/bitunion.hh"
 
+namespace gem5
+{
+
 enum
 {
     SMMU_SECURE_SZ = 0x184, // Secure regs are within page0
@@ -407,4 +410,6 @@ enum
     SMMU_MAX_TRANS_ID = 64
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_DEFS_HH__ */

src/dev/arm/smmu_v3_deviceifc.cc

@@ -42,6 +42,9 @@
 #include "dev/arm/smmu_v3.hh"
 #include "dev/arm/smmu_v3_transl.hh"
 
+namespace gem5
+{
+
 SMMUv3DeviceInterface::SMMUv3DeviceInterface(
     const SMMUv3DeviceInterfaceParams &p) :
     ClockedObject(p),
@@ -261,3 +264,5 @@ SMMUv3DeviceInterface::drain()
     }
     return DrainState::Drained;
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3_deviceifc.hh

@@ -48,6 +48,9 @@
 #include "params/SMMUv3DeviceInterface.hh"
 #include "sim/clocked_object.hh"
 
+namespace gem5
+{
+
 class SMMUTranslationProcess;
 class SMMUv3;
 class SMMUDevicePort;
@@ -133,4 +136,6 @@ class SMMUv3DeviceInterface : public ClockedObject
     void sendRange();
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_DEVICEIFC_HH__ */

src/dev/arm/smmu_v3_events.cc

@@ -39,6 +39,9 @@
 
 #include "dev/arm/smmu_v3_deviceifc.hh"
 
+namespace gem5
+{
+
 void
 SMMUDeviceRetryEvent::process()
 {
@@ -50,3 +53,5 @@ SMMUDeviceRetryEvent::name() const
 {
     return smmuIfc.name() + ".device_retry_event";
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3_events.hh

@@ -41,6 +41,9 @@
 #include <base/types.hh>
 #include <sim/eventq.hh>
 
+namespace gem5
+{
+
 class SMMUv3DeviceInterface;
 
 class SMMUDeviceRetryEvent : public Event
@@ -61,4 +64,6 @@ class SMMUDeviceRetryEvent : public Event
     { return "DeviceRetryEvent"; }
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_EVENTS_HH__ */

src/dev/arm/smmu_v3_ports.cc

@@ -41,6 +41,9 @@
 #include "dev/arm/smmu_v3.hh"
 #include "dev/arm/smmu_v3_deviceifc.hh"
 
+namespace gem5
+{
+
 SMMURequestPort::SMMURequestPort(const std::string &_name, SMMUv3 &_smmu) :
     RequestPort(_name, &_smmu),
     smmu(_smmu)
@@ -174,3 +177,5 @@ SMMUATSDevicePort::recvTimingReq(PacketPtr pkt)
 {
     return ifc.atsRecvTimingReq(pkt);
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3_ports.hh

@@ -41,6 +41,9 @@
 #include "mem/qport.hh"
 #include "mem/tport.hh"
 
+namespace gem5
+{
+
 class SMMUv3;
 class SMMUv3DeviceInterface;
 
@@ -138,4 +141,6 @@ class SMMUATSDevicePort : public QueuedResponsePort
     virtual ~SMMUATSDevicePort() {}
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_PORTS_HH__ */

src/dev/arm/smmu_v3_proc.cc

@@ -43,6 +43,9 @@
 #include "dev/arm/smmu_v3.hh"
 #include "sim/system.hh"
 
+namespace gem5
+{
+
 SMMUProcess::SMMUProcess(const std::string &name, SMMUv3 &_smmu) :
     coroutine(NULL),
     myName(name),
@@ -209,3 +212,5 @@ SMMUProcess::run(PacketPtr pkt)
     assert(*coroutine);
     return (*coroutine)(pkt).get();
 }
+
+} // namespace gem5

src/dev/arm/smmu_v3_proc.hh

@@ -46,6 +46,9 @@
 #include "base/types.hh"
 #include "mem/packet.hh"
 
+namespace gem5
+{
+
 class SMMUv3DeviceInterface;
 
 /*
@@ -132,4 +135,6 @@ class SMMUProcess : public Packet::SenderState
     const std::string name() const { return myName; };
 };
 
+} // namespace gem5
+
 #endif /* __DEV_ARM_SMMU_V3_PROC_HH__ */

src/dev/arm/smmu_v3_ptops.cc

@@ -40,6 +40,9 @@
 #include "base/bitfield.hh"
 #include "base/logging.hh"
 
+namespace gem5
+{
+
 bool
 V7LPageTableOps::isValid(pte_t pte, unsigned level) const
 {
@@ -421,3 +424,5 @@ V8PageTableOps64k::lastLevel() const
 {
     return 3;
 }
+
+} // namespace gem5