diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 04b5cd409b..5d2ed902d2 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -463,8 +463,9 @@ void
 TLB::flush(const TLBIIPA &tlbi_op)
 {
     assert(!isStage2);
-    stage2Tlb->_flushMva(tlbi_op.addr, 0xbeef, tlbi_op.secureLookup,
-        true, tlbi_op.targetEL, false);
+
+    // Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
+    stage2Tlb->flush(tlbi_op.makeStage2());
 }
 
 void
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index cab0e52ae5..ce72dfbca3 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -292,6 +292,13 @@ class TLBIIPA : public TLBIOp
 
     void operator()(ThreadContext* tc) override;
 
+    /** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
+    TLBIMVAA
+    makeStage2() const
+    {
+        return TLBIMVAA(EL1, secureLookup, addr);
+    }
+
     Addr addr;
 };